similar to: [LLVMdev] adding (dwarf) unwind table emission to ARM llc backend

On 08/26/2010 13:17, Dale Johannesen wrote: >>> Insn before the error: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>, >>> %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ... >> >> Odd. I thought TCReturn was being lowered. At any rate can you file >> a bug with the .ll file that causes this? > > It should be getting

On Aug 26, 2010, at 11:34 PMPDT, Yuri wrote: > On 08/26/2010 13:17, Dale Johannesen wrote: >>>> Insn before the error: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>, >>>> %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ... >>> >>> Odd. I thought TCReturn was being lowered. At any rate can you >>> file a bug

On Aug 27, 2010, at 10:49 AM, Dale Johannesen wrote: > > On Aug 26, 2010, at 11:34 PMPDT, Yuri wrote: > >> On 08/26/2010 13:17, Dale Johannesen wrote: >>>>> Insn before the error: TCRETURNri64 %RAX<kill>, 0, %RDI<kill>, %RAX<imp-def,dead>, %RDI<imp-def,dead>, %RSP<imp-use>, ... >>>> >>>> Odd. I thought

On Aug 26, 2010, at 12:59 PMPDT, Eric Christopher wrote: > On Aug 26, 2010, at 12:25 PM, Yuri wrote: >> On 08/26/2010 11:53, Eric Christopher wrote: >>> Could you get it to print out the instruction when it happens? >>> (just change the line above the error message to print it out to >>> errs()). >>> >>> It basically means that a pseudo

On Aug 27, 2010, at 11:00 AMPDT, Eric Christopher wrote: >>> >>> For some reason I am getting this error even when I only have an >>> empty 'main' function. So I couldn't create .ll file reproducing >>> it and I have to debug myself. >>> >>> The function causing the problem is stub created in >>> JIT::runFunction:

Hi All, When seeing the title "Prolog/Epilog Code Insertion", I'd expect something about XXXFrameLowering.cpp (particular about emitPrologue/emitEpilogue). But the document [1] is about unwind. Is it placed at the right place/section? Thanks. [1] http://llvm.org/docs/CodeGenerator.html#prolog-epilog-code-insertion Regards, chenwj -- Wei-Ren Chen (陳韋任) Homepage:

On 08/26/2010 11:53, Eric Christopher wrote: > Could you get it to print out the instruction when it happens? (just change the line above the error message to print it out to errs()). > > It basically means that a pseudo wasn't lowered to something that the jit can output before the jit was run. Is this on ToT? > Insn before the error: TCRETURNri64 %RAX<kill>, 0,

On Aug 26, 2010, at 12:25 PM, Yuri wrote: > On 08/26/2010 11:53, Eric Christopher wrote: >> Could you get it to print out the instruction when it happens? (just change the line above the error message to print it out to errs()). >> >> It basically means that a pseudo wasn't lowered to something that the jit can output before the jit was run. Is this on ToT? >>

Hello, find enclosed a first patch for adding tail call optimizations for thumb1 targets. I assume that this list is the right place for publishing patches for review? Since this is my first proposal for LLVM, I'd very much appreciate your feedback. What the patch is meant to do: For Tail calls identified during DAG generation, the target address will be loaded into a register by use

Hi list, I am trying to implement the technique outlined in the following paper: http://www.cs.umd.edu/~mwh/papers/martin10ownership.html in LLVM. My approach so far involves the use of an IR level transform (via runOnFunction) to identify memory loads and stores. One thing I need to do (I am pretty sure I need to do it at least) is automatically mark each stack frame as "owned" by the

Hello, I want to find information/documentation on how reorganize stack frame (add other information, etc.) & how add new calling convention into ARM backend? I think it is needed to modify lowering of CALL, RET & FORMAL_ARGUMENT instruction, and also to modify emitPrologue & emitEpilogue functions. What are the others things to modify in order to realize my

Hi all Ups, I'm really sorry for that previous message, I've sent it by mistake. So let me write it once more. I've been working for some time now on a backend for our CPU. However I couldn't figure out how to implement some stuff. I'd appreciate your help with these. First thing is return address saving. To do that, first I have to copy it to a general purpose register. I

On Thu, Apr 15, 2010 at 3:40 AM, Artur Pietrek <pietreka at gmail.com> wrote: > Hi all > Ups, I'm really sorry for that previous message, I've sent it by mistake. > > So let me write it once more. > > I've been working for some time now on a backend for our CPU. However I > couldn't figure out how to implement some stuff. > I'd appreciate your help

Hi All, For various obscure reasons I'd like to detect the condition when X86 CALL instruction immediately precedes a function epilogue in the final emitted code, and insert a NOP between them if that happens. My initial attempt at it looked like this: MachineBasicBlock& MBB; MachineBasicBlock::iterator MBBI; <-- points to where the epilogue would be inserted if (MBBI != MBB.begin()

Dale: Yes, there were a number of postings in March. The issue seemed to not have been fully resolved but I added "i686-pc-linux-gnu" to the end of my command line and now the whole thing compiles. I cannot find a llvm-gcc binary in my install directory, all I have is gcc which reports: ../export/bin/gcc -dumpmachine i686-pc-linux-gnu It turns out I can generate llvm assembler output

Implementing tail call opt could look like the following: 0.)a fast calling convention (maybe use the current CallingConv::Fast, or create a CallingConv::TailCall) 1.) lowering of formal arguments like for example x86_LowerCCCArguments in stdcall mode we need to make sure that later mentioned CALL_CLOBBERED_REG is not used (remove it from available registers in callingconvention for

On 7/8/11 4:09 PM, Andrew Ruef wrote: > Hi list, > > I am trying to implement the technique outlined in the following > paper: http://www.cs.umd.edu/~mwh/papers/martin10ownership.html > <http://www.cs.umd.edu/%7Emwh/papers/martin10ownership.html> in LLVM. > My approach so far involves the use of an IR level transform (via > runOnFunction) to identify memory loads and

Hi Andrew, thanks for answering On Thu, Apr 15, 2010 at 3:35 PM, Andrew Lenharth <andrewl at lenharth.org>wrote: > On Thu, Apr 15, 2010 at 3:40 AM, Artur Pietrek <pietreka at gmail.com> wrote: > > Hi all > > Ups, I'm really sorry for that previous message, I've sent it by mistake. > > > > So let me write it once more. > > > > I've

I investigated the MachineFunctionPass (that is runOnMachineFunction, I believe). In my experimentation it didn't seem that the MachineFrameInfo was populated (it consistently said that the stack depth was 0, for example). I might have been doing something wrong? On Fri, Jul 8, 2011 at 5:21 PM, John Criswell <criswell at illinois.edu> wrote: > On 7/8/11 4:09 PM, Andrew Ruef wrote:

On May 28, 2008, at 5:22 PM, robert muth wrote: > I have problem compiling the gcc frontend. > Almost everything seems to compile but at the very end > when crt startup files are compiled, the assembler complains > about bad registers. > Any idea what I am doing wrong? > Thanks, > Robert It looks like your assembler is being invoked in 32-bit mode. Other people have had