similar to: [LLVMdev] subregs in trivial coalescing

On Sep 21, 2010, at 2:45 PMPDT, John Thompson wrote: > fatal error: error in backend: Ran out of registers during register allocation! > Please check your inline asm statement for invalid constraints: > INLINEASM <es:>, 0, 10, %reg16396<def>, 10, %reg16397<def>, 10, %reg16398<def>, 10, %reg16399<def>, 10, %reg16400<def>, 10, %reg16401<def>,10,

Dale, Sorry, I see you did say I should run the gcc tests. I apologize for forgetting this. I'll work on getting them to run here. Chris et. all, I have a fix for the assertion failure in the enclosed llvmmultalt8.patch file. I didn't realize the input constraints could have different numbers of alternatives from the outputs, which now makes sense. The pr20314-2.c file now compiles

hello, I'm suprised that an SRC.RPM from the rhel5 repo needs a file from FC7. I grabbed rpmdevtools from http://download.fedora.redhat.com/pub/epel/5/ it rebuilds fine as EL5, but when I go to install it, it requires a version of rpm-build higher than the C5 base version (4.4.2-37) --------------------- grab dependencies ------------- $ rpm -qpR rpmdevtools-6.1-0.1.noarch.rpm ...

Hi Borja, On Jul 10, 2012, at 6:26 PM, Borja Ferrer wrote: > Hello, > > I would like to know if there's a way of setting the callee-saved register list inside getCalleeSavedRegs() to make the PEI pass save/restore only one half of a register pair if the other half is not being used, instead of saving the whole pair. Here is an example of what I try to explain to make things more

LLVM can model some quite complicated register banks now, and we even use registers to model some encoding constraints. For example, a few ARM instructions like strexd have two register operands that must be an aligned pair of consecutive GPR registers (like r0, r1). This constraint is modeled with the GPRPair register class containing R0_R1, R2_R3, ... pseudo-registers. Sometimes ISAs also

Jakob, I've implemented a patch that reworks the MCRegAliasIterator to dynamically compute the register aliases. The size reduction in the RegDiffLists are rather dramatic. Here are a few size differences for MCTargetDesc.o files (before and after) in bytes: R600 - 36160B - 11184B - 69% reduction ARM - 28480B - 8368B - 71% reduction Mips - 816B - 576B - 29% reduction One side effect of

Does anyone know exactly what ComposerIndices in Target.td is all about? I see just one place where it's used in X86 but it's not clear from the comments in Target.td and it's one usage, exactly what this feature is about. Tia. Reed

Hi, we are still trying to properly connect a Tenovis PBX to an Asterisk server (asterisk 1.2.6, libpri 1.2.2, zaptel 1.2.5, Digium Wildcard TE110P), this time with QSIG. Calling from a Tenovis phone to a SIP phone (i.e. traditional phone -> Tenovis PBX -> QSIG -> Asterisk -> SIP phone) works with the following messages: --- Don't know what to do if second ROSE component is of

On 05/16/2017 11:57 AM, Daniel Sanders wrote: >> If that's right, one possible fix would be to rename some of the subregister indices but that's likely to be quite painful. I'll have a think and see if I can come up with something nicer. > > I haven't been able to come up with a better answer for this, just an alternate choice as to where the complexity is. If we were

On 5/16/2013 11:17 AM, Jakob Stoklund Olesen wrote: > > Would this TRI function solve your problem? >[...] > /// > /// Covering = getCoveringLanes(); > /// MaskA = getSubRegIndexLaneMask(SubA); > /// MaskB = getSubRegIndexLaneMask(SubB); > /// > /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by > /// SubB.

On Fri, 2019-08-30 at 10:03 -0700, Quentin Colombet wrote: > > On Aug 30, 2019, at 8:31 AM, Jesper Antonsson via llvm-dev < > > llvm-dev at lists.llvm.org> wrote: > > > > Hi, > > > > After dead-mi-elimination I'm experiencing a machine verifier > > failure > > at this virtual subregister write: > > > > %5.sub1 = COPY undef

Hi, I'm stuck trying to fix a variety of problems that occur with undef subregisters when the register coalescer eliminates identity copies. The fundamental problem is complexity from the fact that undef values are a special case since they don't have an associated VNInfo/Segment unless the value is used across blocks. For example, in this case, %0 has 2 subregisters sub0 and sub1:

Hi, After dead-mi-elimination I'm experiencing a machine verifier failure at this virtual subregister write: %5.sub1 = COPY undef %11 The machine verifier essentially complains that the rest of the register is undefined (a subregister write implies a "read" of the other parts). So the problem is that dead-mi-elimination has removed the previously existing defines of %5.sub0.

Hello, I would like to know if there's a way of setting the callee-saved register list inside getCalleeSavedRegs() to make the PEI pass save/restore only one half of a register pair if the other half is not being used, instead of saving the whole pair. Here is an example of what I try to explain to make things more clear: Suppose this situation where we have a register file of 8bit regs, and

Yes, the arch is just as you said, something like AMD GPU, but Intel GPU don't have separate register file for 'scalar/vector'. In fact my idea of defining the register tuples was borrowed from SIRegisterInfo.td in AMD GPU. But seems that AMD GPU mainly support i32/i64 register type, while Intel GPU also support byte/short register type. So I have to start defining the registers from

Hi, I can’t seem to find a solution for my last VM issue. I have distorted sound, when I play the Windows 10 device test sound. Only the Windows sound is affected. Mpd of the host is playing just fine meanwhile. I am using ich9 as emulated card, which is detected and installed correctly. The VM is using vfio-igd passthrough, so vnc or spice are not used. I tried to match the Windows driver

I don't wish to install R by rpm. I need to know what Fedora rpms I need to install to give me the capability to install R using the tar.gz source file as I've done for years. On previous occasions when I've installed Fedora, I've used the DVD which has thousands of RPMs. Lately I've installed Fedora 15 from the Live CD which has a lot fewer and so a lot of necessary stuff

I don't wish to install R by rpm. I need to know what Fedora rpms I need to install to give me the capability to install R using the tar.gz source file as I've done for years. On previous occasions when I've installed Fedora, I've used the DVD which has thousands of RPMs. Lately I've installed Fedora 15 from the Live CD which has a lot fewer and so a lot of necessary stuff

On Sep 20, 2010, at 9:40 PMPDT, John Thompson wrote: > Thanks, Stuart. Sorry, I had some left-over editing cruft in my email. From Googling runtest, I had found dejagnu, which I'd heard some folks were using over there, so I used the local package manager to install it. But from what you said I went ahead and got the dejagnu sources and built it, but had problems in running make

Hi Tom, The output: Added VReg_64(explicit) Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64) is saying that VS_32 was added because VReg_64 was explicitly specified and that while inspecting VS_32, it noticed that every register in VS_32 was a subregister of a register from VReg_64 using a single common subregister index. I've added some more tracing to my local copy and