similar to: [LLVMdev] Hidden function (that calls main) ?

Is this the configuration you would give for an iphone? -Puyan ----- Original Message ----- From: "Jim Grosbach" <grosbach at apple.com> To: "Puyan Lotfi" <puyan at gatech.edu> Cc: llvmdev at cs.uiuc.edu Sent: Wednesday, February 17, 2010 4:42:37 PM GMT -05:00 US/Canada Eastern Subject: Re: [LLVMdev] Need help getting LLVM JIT running on ARM Specifying --host,

>From a cached version of the Getting Started Guide, I have found: "GCC 3.4.4 (CodeSourcery ARM 2005q3-2): this compiler miscompiles LLVM when building with optimizations enabled. It appears to work with "make ENABLE_OPTIMIZED=1 OPTIMIZE_OPTION=-O1" or build a debug build." I'm trying that now. -Puyan On Sun, Feb 21, 2010 at 1:22 AM, Rajika Kumarasiri <rajika at

Puyan, There is a doc on the document page which describe the list of broken GCCs. You'll need to check it once the docs are online. Rajika On Sun, Feb 21, 2010 at 11:33 AM, Puyan Lotfi <puyan at gatech.edu> wrote: > Hi > > Does there exist a list of relative compile times for source files in LLVM? > I am doing a build for ARM on an actual ARM device, and >

Specifying --host, --build and --target should work. For example, $ configure --host=arm-apple-darwin10 --build=i686-apple-darwin10 --target=arm-apple-darwin10 --enable-targets=arm -Jim On Feb 17, 2010, at 12:26 PM, Puyan Lotfi wrote: > Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? > I want to use the LLVM JIT on ARM for a class

Hi Does there exist a list of relative compile times for source files in LLVM? I am doing a build for ARM on an actual ARM device, and CodeGenDAGPatterns.cpp is taking a really long time to compile (it's been like 20 minutes or more). I don't even get an error. All the files before it compile pretty quickly but this file in particular just won't finish. The version of gcc I have on

Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? I want to use the LLVM JIT on ARM for a class project this semester. I have built and/or installed a few different gcc arm (arm-linux, and also one that is arm-elf) toolchains, and have had trouble getting LLVM 2.6 to configure and compile using the --host and --build switches of the config. If there

Hi I am not sure if it is possible to do something similar to what the LLVM pass framework offers (via the opt program) but in the JIT instead (when running lli). Is it possible to do any kind of online profiling (or optimization) of dynamically compiler code similar to writing an opt style code pass module? Or would I have to change a lot of stuff in the JIT? Thanks -Puyan

So I got very mixed results. With the CallGraphSCCPass, both `addRequired<DominatorTreeWrapperPass>` and `addRequired<MemoryDependenceAnalysis>` fail at runtime. The LLVM core has just two CallGraphSCCPasses and neither uses neither analyses, so it's hard to find a valid example. I transformed the pass into a ModulePass, using scc_iterator as shown in CGPassManager to process

Hi I am interested to know: are there are any LLVM targets in the works for Nvidia's PTX ISA? Also if anyone knows about Ocelot (a project done by some students at my school): it does the opposite of what I am trying to do (translates PTX to LLVM IR to run Cuda kernels on the CPU). Thanks in advance. -Puyan

On 1/10/06, Chris Lattner <sabre at nondot.org> wrote: > Interesting approach. :) Thanks. > Comments below, with ***'s before the notes: > +class LoopPass : public Pass {}; // Temporary. > > *** I wouldn't worry about loop passes yet. Sure. > +class PassUnit { > + Pass *pass; > + > + enum Traversal { > + LINEAR, // Standard top down

On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: > Hi > > I am interested to know: are there are any LLVM targets in the works > for Nvidia's PTX ISA? > > Also if anyone knows about Ocelot (a project done by some students at > my school): it does the opposite of what I am trying to do (translates > PTX to LLVM IR to run Cuda kernels on the CPU). I don't know of

Hi, My name is Puyan and I've been exploring ways to improve the state of instruction level diffing using llvm and MIR. Below is a proposal for a new llvm tool meant to address issues encountered when diffing at the machine level. I'm eager to hear the community's feedback. Thanks PL mir-canon: A new tool for canonicalizing MIR for cleaner diffing. Problem Statement and

I'm writing a front end for an existing interpreted language with slightly odd semantics for primitive values. Similar to the values in a database table, any value could be null, even for non-pointer types. For example a boolean variable could be true, false, or null. To model this behaviour, I'm passing an {i1, [type]} around for every numeric type. And using insertvalue / extractvalue

Can we use %% for vregs? Seems slightly easier to remember %/%% than $/%. Also, %eax and $some_symbol are already familiar from typical assembly syntax and we probably don't want to break that association. It's all a bikeshed, but being more consistent with assembly is probably a win. -- Sean Silva On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" < llvm-dev at

When we discussed this our line of thought was like this: - LLVM IR already uses %name for SSA values which is closer to what a vreg is than to what a physreg is. It would be neat to draw that parallel to llvm IR. - We wanted another sigil for physregs so they are easy to differentiate from vregs to allow people to differentiate vregs/physregs even if they don't know all the physreg names of

Hi,all Recently,I write some code to implement the following funtions: I make use the codes of "llvm-dis" to disassemble the bitcode file and do some change on it,after that ,"my llvm-as" assembles the changed file to generate a bitcode file. But I got a "corrupted double-linked list" error when "my llvm-as" works,however,when I do nothing on the

On Mon, Jan 8, 2018 at 2:27 PM, Matthias Braun <mbraun at apple.com> wrote: > When we discussed this our line of thought was like this: > > - LLVM IR already uses %name for SSA values which is closer to what a vreg > is than to what a physreg is. It would be neat to draw that parallel to > llvm IR. > - We wanted another sigil for physregs so they are easy to differentiate

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >> Hi, >> >> >>

I have a bitcode file Y that has a symbol __isoc99_fscanf in it. When I disassemble the bitcode, the symbol is written as "\01__isoc99_fscanf". I am wondering where this symbol is coming from? I grep'ed throughout /usr on my machine for both names, and I only found __isoc99_fscanf, without the special character in front. Regardless of where the symbol is coming from, I am

On 29 May 2010 02:43, Ryan M. Lefever <lefever at illinois.edu> wrote: > I have a bitcode file Y that has a symbol  __isoc99_fscanf in it.  When > I disassemble the bitcode, the symbol is written as > "\01__isoc99_fscanf".  I am wondering where this symbol is coming from? >  I grep'ed throughout /usr on my machine for both names, and I only > found