similar to: [LLVMdev] Complex regalloc contraints

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Complex regalloc contraints"

2010 Sep 07
0
[LLVMdev] Complex regalloc contraints
On Sep 7, 2010, at 3:01 AM, Carlos Sanchez de La Lama wrote: > The machine I am targeting has some special requirements for some > operations, say: > > ADD or1, ir1, r5 > > would add ir1 (input reg 1) and r5 and put the result in or1 (output reg > 1). The point id that input and output regs have to go paired (this > meaning an addition of ir1 with whatever always goes to
2010 Sep 08
3
[LLVMdev] Complex regalloc contraints
Hi Carlos, Jakob, The PBQP allocator was designed to support a very wide range of constraints, and can handle something like this easily. Say you have 4 of these orX/irX registers, then for any pair of virtual registers used in such an add instruction you would add the following constraint matrix to the PBQP instance: [ 0 inf inf inf ] [ inf 0 inf inf ] [ inf inf 0 inf ] [ inf inf inf 0
2010 Sep 08
0
[LLVMdev] Complex regalloc contraints
On Sep 7, 2010, at 6:27 PM, Lang Hames wrote: > The design I have in mind is this: We add a method to TargetRegisterInfo which returns a PBQPProblemBuilder for the target architectures. I implement a base PBQPProblemBuilder by simply lifting the current construction process out of the PBQP allocator and into its own class. Anyone (such as yourself, Carlos) who wants to represent more esoteric
2010 Sep 09
1
[LLVMdev] Complex regalloc contraints
Hi Jakob, That's a good point. I'll factor out the problem builder in the next couple of days and drop a mail to the list explaining how to write extensions. Cheers, Lang. On Thu, Sep 9, 2010 at 12:21 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Sep 7, 2010, at 6:27 PM, Lang Hames wrote: > > The design I have in mind is this: We add a method to
2009 Jan 07
2
Plotting a graph for every Level of a Factor
Hello, I'm sorry if this seems similar to my last post but I thought it was significantly different to warrent a new thread. Using the dataset below, is there a way to generate a bar/line plot for the TACC/Catch of every lvl of stock? i.e. OR1,OR3,OR5. The picture at the bottom of this post is an example of the bar/line plot for OR1 which was generated when OR1 was the only stock in the
2013 Oct 31
0
[LLVMdev] loop vectorizer
>> What needs to be done (on a high level) in order to have the auto vectorizer succeed on the test function as given erlier? > Maybe you could rewrite the loop in a way that will expose contiguous memory accesses. Is this something you could do ? > Hi Nadav, the only option I see is to unroll the loop by hand. Since the array access is consecutive over 4 loop iterations I gave it a
2013 Oct 31
2
[LLVMdev] loop vectorizer
On Oct 30, 2013, at 6:10 PM, Frank Winter <fwinter at jlab.org> wrote: > the only option I see is to unroll the loop by hand. Since the array access is consecutive over 4 loop iterations I gave it a try and unrolled the loop by a factor of 4. Which gives the following array accesses: > > loop iter 0: > index_0 = 0 index_1 = 4 > index_0 = 1 index_1 = 5 > index_0 = 2
2013 Jun 11
1
Help needed in feature extraction from two input files
Hi, Try this: lines1<- readLines(textConnection("gene1 or1|1234 or3|56 or4|793 gene4 or2|347 gene5 or3|23 or7|123456789")) lines2<-readLines(textConnection(">or1|1234 ATCGGATTCAGG >or2|347 GAACCTATCGGGGGGGGAATTTATATATTTTA >or3|56 ATCGGAGATATAACCAATC >or3|23 AAAATTAACAAGAGAATAGACAAAAAAA >or4|793 ATCTCTCTCCTCTCTCTCTAAAAA >or7|123456789
2009 Jan 07
1
Bar Plot with Connected Points on 1 Y-Axis
Hi Everyone, Have created a bar plot of the data below using the following code: barplot(TACC,space=0,names.arg=Year). I now want to add a series of connected points to represent the catch. I tried to do this using line(Catch) or points(Catch), however both of these commands result in each data point being aligned with the right edge of each bar. I need them to be solid points in the centre of
2014 Aug 21
2
pregunta
Buenas noches Javier y José, Estoy en contra de usar attach(), asi que propongo la siguiente alternativa con with(): # paquete require(epicalc) # los argumentos en ... pasan de epicalc:::cc # ver ?cc para mas informacion foo <- function(var1, var2, var3, ...){ or1 <- cc(var1, var2, ...) or2 <- cc(var1, var3, ...) list(or1 = or1, or2 = or2) } # datos x <-
2012 Aug 01
3
Neuralnet Error
I require some help in debugging this code  library(neuralnet) ir<-read.table(file="iris_data.txt",header=TRUE,row.names=NULL) ir1 <- data.frame(ir[1:100,2:6]) ir2 <- data.frame(ifelse(ir1$Species=="setosa",1,ifelse(ir1$Species=="versicolor",0,""))) colnames(ir2)<-("Output") ir3 <- data.frame(rbind(ir1[1:4],ir2))
2013 Oct 30
2
[LLVMdev] loop vectorizer
The debug messages are misleading. They should read “trying to vectorize a list of …”; The problem is that the SCEV analysis is unable to detect that C[ir0] and C[ir1] are consecutive. Is this loop from an important benchmark ? Thanks, Nadav On Oct 30, 2013, at 11:13 AM, Frank Winter <fwinter at jlab.org> wrote: > The SLP vectorizer apparently did something in the prologue of the
2013 Oct 30
2
[LLVMdev] loop vectorizer
The loop vectorizer seems to be not able to vectorize the following code: void bar(std::uint64_t start, std::uint64_t end, float * __restrict__ c, float * __restrict__ a, float * __restrict__ b) { const std::uint64_t inner = 4; for (std::uint64_t i = start ; i < end ; ++i ) { const std::uint64_t ir0 = ( (i/inner) * 2 + 0 ) * inner + i%4; const std::uint64_t ir1 = ( (i/inner)
2014 Mar 03
2
Re: 'virsh capabilities' on Debian Wheezy-amd64 reports different cpu to Wheezy-i386 (on same hardware)
On 03/03/2014 10:55, Martin Kletzander wrote: > On Mon, Mar 03, 2014 at 10:47:03AM +0000, Struan Bartlett wrote: >> On 03/03/2014 10:44, Martin Kletzander wrote: >>> On Mon, Mar 03, 2014 at 10:30:11AM +0000, Struan Bartlett wrote: >>>> Hi Martin >>>> >>>> Thanks for your response. Here's the output of that grep: >>>>
2014 Mar 03
2
Re: 'virsh capabilities' on Debian Wheezy-amd64 reports different cpu to Wheezy-i386 (on same hardware)
On 03/03/2014 13:42, Martin Kletzander wrote: > On Mon, Mar 03, 2014 at 11:15:51AM +0000, Struan Bartlett wrote: >> On 03/03/2014 10:55, Martin Kletzander wrote: >>> On Mon, Mar 03, 2014 at 10:47:03AM +0000, Struan Bartlett wrote: >>>> On 03/03/2014 10:44, Martin Kletzander wrote: >>>>> On Mon, Mar 03, 2014 at 10:30:11AM +0000, Struan Bartlett wrote:
2010 Jan 27
1
Possible bug in fisher.test() (PR#14196)
# is there a bug in the calculation of the odds ratio in fisher.test? # Nicholas Horton, nhorton at smith.edu Fri Jan 22 08:29:07 EST 2010 x1 = c(rep(0, 244), rep(1, 209)) x2 = c(rep(0, 177), rep(1, 67), rep(0, 169), rep(1, 40)) or1 = sum(x1==1&x2==1)*sum(x1==0&x2==0)/ (sum(x1==1&x2==0)*sum(x1==0&x2==1)) library(epitools) or2 = oddsratio.wald(x1, x2)$measure[2,1] or3 =
2013 Oct 30
0
[LLVMdev] loop vectorizer
The SLP vectorizer apparently did something in the prologue of the function (where storing of arguments on the stack happens) which then got eliminated later on (since I don't see any vector instructions in the final IR). Below the debug output of the SLP pass: Args: opt -O1 -vectorize-slp -debug loop.ll -S SLP: Analyzing blocks in _Z3barmmPfS_S_. SLP: Found 2 stores to vectorize. SLP:
2006 Nov 15
1
Composition of NEAR and OR
The following piece of code triggers an 'unimplemented' exception with the message: "Can't use NEAR/PHRASE with a subexpression containing NEAR or PHRASE" Xapian::Query or1(Xapian::Query::OP_OR, Xapian::Query("one"), Xapian::Query("two")); Xapian::Query or2(Xapian::Query::OP_OR, Xapian::Query("three"),
2014 Aug 21
2
pregunta
Estimados Estoy entrenando hacer funciones que respondan a comandos, en esta caso en la salida gráfica se observa que dice : Exposure=var3 y outcome=var 1 quisiéramos que se reflejan los nombres de la base de datos : var1=estado, var2=cake, var3=chocolate Espero haberme explicado adecuadamente Adjunto tabla con datos #################################### #Comando que llama
2010 May 11
2
[LLVMdev] Need help for my PBQP regAlloc proj in llvm....
Hello, we are currently working on my project that aims at improving the register allocation scheme by identifying if the interference graphs are chordal or not. we are working on the llvm compiler .we are forcing the compiler to use PBQP register allocation scheme by an option of ' ' regalloc=pbqp ' during the execution of prgm. we have been succesfull in accessing the interference