similar to: [LLVMdev] Is structural analysis pass available?

On 07/20/10 02:24, Jianzhou Zhao wrote: > Hi, > > Is the structural analysis pass discussed in > http://comments.gmane.org/gmane.comp.compilers.llvm.devel/30213 still > available to download? Hi, I recently proposed the RegionInfo pass for LLVM. It is not a complete structural analysis pass, however it builds an sese region tree and can probably be extended to classify the

On Thu, Nov 11, 2010 at 8:28 AM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: > Hi all, > > http://www.llvm.org/docs/ProgrammersManual.html#BuildRecType suggests > us to define recursive types via opaque and refine. Since LLVM has > structural types, %rt = type { %rt* } and %rt1 = type { %rt* } should > be same structurally. I tested the following code, > > %rt =

On Wed, Jan 4, 2012 at 12:10 PM, David Gardner <daveg at xmos.com> wrote: > Jianzhou Zhao <jianzhou <at> seas.upenn.edu> writes: >> The documents say that all the aa analysis are chained, and give an >> example like opt -basicaa -ds-aa -licm. In this case, does ds-aa >> automatically call basicaa for the case when ds-aa can only return >> MayAlias? This

Hi all, http://www.llvm.org/docs/ProgrammersManual.html#BuildRecType suggests us to define recursive types via opaque and refine. Since LLVM has structural types, %rt = type { %rt* } and %rt1 = type { %rt* } should be same structurally. I tested the following code, %rt = type { %rt* } %rt1 = type { %rt* } define i32 @main() nounwind { entry: %0 = alloca %rt ;

I noticed the patch was already merged into the current LLVM language reference manual with new memory instructions, fence, cmpxchg and atomicrmw. Will the instructions be available in LLVM 3.0? On Mon, Jul 18, 2011 at 8:22 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > There was some discussion a while back about adding a C++0x-style > memory model and atomics for LLVM a while

Jianzhou Zhao <jianzhou <at> seas.upenn.edu> writes: > At this level, I can understand how it works. I was confused because I > have been looking at the source code for implementing them. All the > globalmodref, scev-aa, steenaa and ds-aa are only subclasses of the > AliasAnalysis class, so I cannot see how ds-aa can automatically call > basicaa. There's some magic

Jianzhou Zhao <jianzhou <at> seas.upenn.edu> writes: > The documents say that all the aa analysis are chained, and give an > example like opt -basicaa -ds-aa -licm. In this case, does ds-aa > automatically call basicaa for the case when ds-aa can only return > MayAlias? This looks magic to me. Is this handled by AnalysisGroup > magically? As I understand it, the

On Tue, Jan 3, 2012 at 4:55 PM, Chris Lattner <clattner at apple.com> wrote: > On Jan 3, 2012, at 1:53 PM, Jianzhou Zhao wrote: >> I see. I asked the question because LLVM provides several alias >> analysis, and I was wondering how to decide which one should be used >> for compiling most programs. >> >> I think the basicaa is the default one, but by looking

On Tue, Jul 6, 2010 at 10:07 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: > On Tue, Jul 6, 2010 at 8:34 PM, Chris Lattner <clattner at apple.com> wrote: >> >> On Jul 6, 2010, at 3:37 PM, Jianzhou Zhao wrote: >> >>> Which semantics is better? I guess both are fine because if we assume >>> these two def's are same, then it is 0 as

C++ and Java memory models impose restrictions for locks and unlocks, such as a thread that releases a lock must acquired the lock, or the number of locks must be larger than the number of unlocks in the same thread... for enabling some optimizations, for example, simplifying trylocks (http://www.hpl.hp.com/techreports/2008/HPL-2008-56.html), and moving some instructions inside lock acquires

On Sun, Jul 31, 2011 at 12:49 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: > I noticed the patch was already merged into the current LLVM language > reference manual with new memory instructions, fence, cmpxchg and > atomicrmw. Will the instructions be available in LLVM 3.0? Hopefully, yes; the implementation is in progress. -Eli

On Mon, Aug 22, 2011 at 3:02 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Mon, Aug 22, 2011 at 11:17 AM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: >> On Mon, Aug 22, 2011 at 1:02 PM, Eli Friedman <eli.friedman at gmail.com> wrote: >>> On Mon, Aug 22, 2011 at 9:55 AM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: >>>> In

Another quick question. In ./bindings/ocaml/Makefile.ocaml, the configurations when ENABLE_OPTIMIZED<>1 are commented, which set -g flag to $(OCAMLC). Is that for back-compatibility to support OCaml < 3.10.0? On Sun, Feb 28, 2010 at 6:48 PM, Erick Tryzelaar <idadesub at users.sourceforge.net> wrote: > On Sun, Feb 28, 2010 at 8:38 AM, Jianzhou Zhao <jianzhou at

In the definition of 'monotonic' ordering, ... "If an address is written monotonically by one thread, and other threads monotonically read that address repeatedly, the other threads must eventually see the write"... Does this mean if a thread does multi-writes monotonically, monotonic reads from other threads should see all of them? But intuitively, it seems to be fine for a

On Sun, Jul 31, 2011 at 7:12 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Sun, Jul 31, 2011 at 12:49 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: >> I noticed the patch was already merged into the current LLVM language >> reference manual with new memory instructions, fence, cmpxchg and >> atomicrmw. Will the instructions be available in LLVM

The current memory model section ends with the following discussions: "Note that in cases where none of the atomic intrinsics are used, this model places only one restriction on IR transformations on top of what is required for single-threaded execution: introducing a store to a byte which might not otherwise be stored to can introduce undefined behavior.... " Why is introducing

On Mon, Aug 22, 2011 at 3:02 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Mon, Aug 22, 2011 at 11:17 AM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: >> On Mon, Aug 22, 2011 at 1:02 PM, Eli Friedman <eli.friedman at gmail.com> wrote: >>> On Mon, Aug 22, 2011 at 9:55 AM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: >>>> In

On Mon, Aug 22, 2011 at 11:17 AM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: > On Mon, Aug 22, 2011 at 1:02 PM, Eli Friedman <eli.friedman at gmail.com> wrote: >> On Mon, Aug 22, 2011 at 9:55 AM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: >>> In the definition of 'monotonic' ordering, >>> ... "If an address is written

On Sun, Jul 31, 2011 at 7:11 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Sun, Jul 31, 2011 at 3:04 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: >> The current memory model section ends with the following discussions: >> >> "Note that in cases where none of the atomic intrinsics are used, this >> model places only one restriction on

On Mon, Aug 22, 2011 at 7:35 PM, Jeffrey Yasskin <jyasskin at google.com> wrote: > On Mon, Aug 22, 2011 at 4:20 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: >> On Mon, Aug 22, 2011 at 6:49 PM, Eli Friedman <eli.friedman at gmail.com> wrote: >>> On Mon, Aug 22, 2011 at 3:40 PM, Jianzhou Zhao <jianzhou at seas.upenn.edu> wrote: >>>> On