similar to: [LLVMdev] Treating function calls as barriers

On Tue, Jun 1, 2010 at 5:13 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Is there a flag to set in Tablegen source so that all function calls act as > instruction barriers. I.e. no instruction can be schedule around a function > call. Do you mean "don't schedule instructions which appear before the call in the source after the call, and vice versa?" There

On Thu, Oct 8, 2009 at 3:59 PM, Devang Patel <devang.patel at gmail.com> wrote: > On Thu, Oct 8, 2009 at 11:28 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: >> >> >>> -----Original Message----- >>> From: Jeffrey Yasskin [mailto:jyasskin at google.com] >>> Sent: Thursday, October 08, 2009 11:09 AM >>> To: Villmow, Micah

Is there a current way to specify that an instruction or function call cannot be duplicated and thus any optimizations that might want to duplicate this instruction would fail? The problem deals with barrier in OpenCL 1.0. One of the conditions of using barrier is that if a barrier exists inside of control flow, every thread in a work-group must execute the barrier instruction(6.11.9).

> -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Wednesday, October 07, 2009 5:50 PM > To: Villmow, Micah > Cc: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Instructions that cannot be duplicated > > On Wed, Oct 7, 2009 at 11:20 AM, Villmow, Micah <Micah.Villmow at amd.com> > wrote: > > Is there a current

> -----Original Message----- > From: Jeffrey Yasskin [mailto:jyasskin at google.com] > Sent: Thursday, October 08, 2009 11:09 AM > To: Villmow, Micah > Cc: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Instructions that cannot be duplicated > > On Thu, Oct 8, 2009 at 10:49 AM, Villmow, Micah <Micah.Villmow at amd.com> > wrote: > > > > >

On Thu, Oct 8, 2009 at 10:49 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > > >> -----Original Message----- >> From: Eli Friedman [mailto:eli.friedman at gmail.com] >> Sent: Wednesday, October 07, 2009 5:50 PM >> To: Villmow, Micah >> Cc: LLVM Developers Mailing List >> Subject: Re: [LLVMdev] Instructions that cannot be duplicated >>

> -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: Monday, November 08, 2010 10:41 AM > To: Villmow, Micah > Cc: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Creating tablegen patterns for intrinsics with > no return value. > > > On Nov 8, 2010, at 10:32 AM, Villmow, Micah wrote: > > > I have intrinsic with no

On Thu, Oct 8, 2009 at 11:28 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > > >> -----Original Message----- >> From: Jeffrey Yasskin [mailto:jyasskin at google.com] >> Sent: Thursday, October 08, 2009 11:09 AM >> To: Villmow, Micah >> Cc: LLVM Developers Mailing List >> Subject: Re: [LLVMdev] Instructions that cannot be duplicated >>

I have intrinsic with no return value and I need to match them to machine instructions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted. Here is my profile/node/pattern. Profile: def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [ SDTCisPtrTy<0>, SDTCisVT<1, i32>,

On Wed, Oct 7, 2009 at 11:20 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Is there a current way to specify that an instruction or function call > cannot be duplicated and thus any optimizations that might want to duplicate > this instruction would fail? No. Anything can be duplicated. That could change, but you would need to make a strong case for why other solutions

With my backend code gen I want to assign calling parameters to a list of registers, but since I'm targeting a virtual instruction set. I don't want to be limited by the number of registers. Is there a way using TableGen to specify just a starting register to assign to for the CallingConv class and then have it just use sequential registers? Micah Villmow Systems Engineer Advanced

Owen/Chandler/etc.., While I have no issue with having a more complete and documented method of submitting backends, the problem is the barrier to entry for some backends is being significantly raised, where they did not exist in the past. In the past AMD has reported issues that we have found from internal development to LLVM, along with patches in some cases. Some have been fixed, but others are

From: Justin Holewinski [mailto:justin.holewinski at gmail.com] Sent: Tuesday, December 13, 2011 10:50 AM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Changes to the PTX calling conventions On Tue, Dec 13, 2011 at 12:54 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote: From: Justin Holewinski [mailto:justin.holewinski

On Nov 8, 2010, at 10:32 AM, Villmow, Micah wrote: > I have intrinsic with no return value and I need to match them to machine instructions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted. Hi Micah, >From your description it sounds like machine dead code elimination is

That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: multiclass instmcRegImm<...> { def rr: inst<...>; def ri: inst<...>; def ir: inst<...>; def ii: inst<...>; } multiclass instmc<...> { defm i8 : instmcRegImm<...>; ^-- repeat for 15

Michah, On Jul 17, 2012, at 7:53 AM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > Owen/Chandler/etc.., > While I have no issue with having a more complete and documented method of submitting backends, the problem is the barrier to entry for some backends is being significantly raised, where they did not exist in the past. In the past AMD has reported issues that we

Ahh yep, thanks for catching that, new patch attached. > -----Original Message----- > From: Hal Finkel [mailto:hfinkel at anl.gov] > Sent: Tuesday, July 31, 2012 1:40 PM > To: Villmow, Micah > Cc: Developers Mailing List > Subject: Re: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> > > Micah, > > I think that your patch is missing the necessary

Possible to add a test case? Micah > -----Original Message----- > From: Sebastian Pop [mailto:spop at codeaurora.org] > Sent: Wednesday, June 20, 2012 1:40 PM > To: Villmow, Micah > Cc: llvmdev at cs.uiuc.edu; llvm-commits at cs.uiuc.edu > Subject: Re: [LLVMdev] How to define macros in a tablegen file? > > On Wed, Jun 20, 2012 at 12:34 PM, Sebastian Pop <spop at

I'm not at the machine that has the changes, but it was failing at index 0. Micah From: Owen Anderson [mailto:resistor at mac.com] Sent: Thursday, April 19, 2012 3:35 PM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output

Micah, One more thing ;) -- llvm::getEnumName in utils/TableGen/CodeGenTarget.cpp -Hal On Tue, 31 Jul 2012 21:02:02 +0000 "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > Ahh yep, thanks for catching that, new patch attached. > > > -----Original Message----- > > From: Hal Finkel [mailto:hfinkel at anl.gov] > > Sent: Tuesday, July 31, 2012 1:40 PM