Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Scheduled Instructions go missing"
2010 Feb 04
1
[LLVMdev] Instruction Itineraries
All,
I am working on a scheduler for X86 and would like to
include instruction latencies. It appears that this
information is gathered from instruction itineraries, but
that there isn't an itinerary for X86. I also can't seem
to find documentation on how to add this for X86. Any
pointers would be helpfull.
Aran
-------------- next part --------------
A non-text attachment was
2010 Mar 26
2
[LLVMdev] X86 Target instruction definitions
All,
Where are the SSE instructions defined? Specifically, I
cannot find the def for ADDSDrr.
Aran
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 194 bytes
Desc: This is a digitally signed message part.
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100326/130b2e02/attachment.sig>
2010 Feb 13
1
[LLVMdev] llvm-gcc 4.2
All,
I'm trying to build llvm-gcc 4.2 from svn (as of about a
week ago). I'm getting:
../../llvm-gcc-4.2/libcpp/expr.c: In function 'num_negate':
../../llvm-gcc-4.2/libcpp/expr.c:1114: internal compiler
error: Segmentation fault
Please submit a full bug report,
with preprocessed source if appropriate.
I would like to do some debugging, but I don't see
where
2010 May 07
1
[LLVMdev] Missuse of xmm register on X86-64
All,
I've been working on a new scheduler and have
somehow affected register selection. My problem is that an
xmm register is being used as an index expression.
Specifically,
addss (%xmm1,%rax,4), %xmm0
I like the idea of a floating-point index, but, like the
assembler, I don't know what that means. Any suggestions
on where I should look for a solution to my problem?
2001 Feb 06
2
SCO 5.0.5 (i686-pc-sco3.2v5.0.5), scp and the -n option
Ok, using openssh-SNAP-20010126.tar.gz, two versions of the server both compiled with the
configure commands as below, one with USE_PIPES defined
and one without. This is on SCO OpenServer 5.0.5 (using SCO dev
environment, SCO make, etc.) The client is always linux, openssh
2.3.0p1.
export CCFLAGS='-L/usr/local/lib -I/usr/local/include'
./configure --sysconfdir=/etc/ssh
2016 Jun 29
0
avx512 JIT backend generates wrong code on <4 x float>
Hi Frank,
I recommend trying trunk LLVM. AVX-512 development has been very active recently.
-Hal
----- Original Message -----
> From: "Frank Winter via llvm-dev" <llvm-dev at lists.llvm.org>
> To: "LLVM Dev" <llvm-dev at lists.llvm.org>
> Sent: Wednesday, June 29, 2016 2:41:39 PM
> Subject: [llvm-dev] avx512 JIT backend generates wrong code on <4
2016 Jun 29
2
avx512 JIT backend generates wrong code on <4 x float>
Hi!
When compiling the attached module with the JIT engine on an Intel KNL I
see wrong code getting emitted. I attach a complete exploit program
which shows the bug in LLVM 3.8. It loads and JIT compiles the module
and prints the assembler. I stumbled on this since the result of an
actual calculation was wrong. So, it's not only the text version of the
assembler also the machine
2016 Jun 30
1
avx512 JIT backend generates wrong code on <4 x float>
Hi Hal!
Thanks, but unfortunately it didn't help. The exact same assembler
instructions are generated for both 3.8 (yesterday) and trunk (from today).
So, this really looks like a bug.
Best,
Frank
On 06/29/2016 03:48 PM, Hal Finkel wrote:
> Hi Frank,
>
> I recommend trying trunk LLVM. AVX-512 development has been very active recently.
>
> -Hal
>
> ----- Original
2014 Jul 23
4
[LLVMdev] the clang 3.5 loop optimizer seems to jump in unintentional for simple loops
the clang 3.5 loop optimizer seems to jump in unintentional for simple loops
the very simple example
----
const int SIZE = 3;
int the_func(int* p_array)
{
int dummy = 0;
#if defined(ITER)
for(int* p = &p_array[0]; p < &p_array[SIZE]; ++p) dummy += *p;
#else
for(int i = 0; i < SIZE; ++i) dummy += p_array[i];
#endif
return dummy;
}
int main(int argc, char** argv)
{
2016 Jun 23
2
AVX512 instruction generated when JIT compiling for an avx2 architecture
With LLVM 3.8 the JIT compiler engine generates an AVX512 instruction
although I target an 'avx2' CPU (intel Core I7).
I just downloaded the most recent 3.8 and still it happens.
It happens with this input module:
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define void @module_cFFEMJ(i64 %lo, i64 %hi, i64 %myId, i1 %ordered, i64
%start, i32* noalias align 32
2016 Jun 23
2
AVX512 instruction generated when JIT compiling for an avx2 architecture
On 06/23/2016 12:56 PM, Craig Topper wrote:
> Can you check what value "getHostCPUName" returned?
getHostCPUName() = skylake
>
> On Thu, Jun 23, 2016 at 9:53 AM, Frank Winter via llvm-dev
> <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
>
> With LLVM 3.8 the JIT compiler engine generates an AVX512
> instruction although I
2015 Oct 27
4
How can I tell llvm, that a branch is preferred ?
If I read the llvm language correctly, it doesn't have a way to specify
the preferred branch, correct ? I see nothing in the specs for "branch"
or "switch". And __buildin_expect does nothing, that I am sure of.
Unfortunately llvm has this knack for ordering my one most crucial part
of code exactly the opposite I want to, it does: (x86_64)
cmpq %r15, (%rax,%rdx)
jne
2013 Apr 03
2
[LLVMdev] Packed instructions generaetd by LoopVectorize?
Hi,
I have a question about LoopVectorize. I wrote a simple test case, a dot product loop and found that packed instructions are generated when input arrays are integer, but not when they are float or double.
If I modify the float example in http://llvm.org/docs/Vectorizers.html by adding restrict to the input arrays packed instructions are generated. Although it should not be required I tried
2010 Jan 22
2
[LLVMdev] Exception handling question
2010/1/22 Duncan Sands <baldrick at free.fr>
> Hi James,
>
>
> I've been trying to get a minimal test function to work, which simply
>> invokes _Unwind_RaiseException with a single clean-up landing pad. However.
>> when I run it my personality function is not getting called -
>> _Unwind_RaiseException simply returns apparently doing nothing. Looking at
2015 Jul 29
2
[LLVMdev] x86-64 backend generates aligned ADDPS with unaligned address
When I compile attached IR with LLVM 3.6
llc -march=x86-64 -o f.S f.ll
it generates an aligned ADDPS with unaligned address. See attached f.S,
here an extract:
addq $12, %r9 # $12 is not a multiple of 4, thus for
xmm0 this is unaligned
xorl %esi, %esi
.align 16, 0x90
.LBB0_1: # %loop2
2013 Apr 03
0
[LLVMdev] Packed instructions generaetd by LoopVectorize?
Hi Tyler,
Try adding -ffast-math. We can only vectorize reduction variables if it is safe to reorder floating point operations.
Thanks,
Nadav
On Apr 3, 2013, at 10:29 AM, "Nowicki, Tyler" <tyler.nowicki at intel.com> wrote:
> Hi,
>
> I have a question about LoopVectorize. I wrote a simple test case, a dot product loop and found that packed instructions are
2013 Apr 04
1
[LLVMdev] Packed instructions generaetd by LoopVectorize?
Thanks, that did it!
Are there any plans to enable the loop vectorizer by default?
From: Nadav Rotem [mailto:nrotem at apple.com]
Sent: Wednesday, April 03, 2013 13:33 PM
To: Nowicki, Tyler
Cc: LLVM Developers Mailing List
Subject: Re: Packed instructions generaetd by LoopVectorize?
Hi Tyler,
Try adding -ffast-math. We can only vectorize reduction variables if it is safe to reorder floating
2010 Sep 01
0
[LLVMdev] equivalent IR, different asm
On Sep 1, 2010, at 6:25 AM, Argyrios Kyrtzidis wrote:
> The attached .ll files seem equivalent, but the resulting asm from 'opt-fail.ll' causes a crash to webkit.
> I suspect the usage of registers is wrong, can someone take a look ?
The difference is that there is a shift right after the multiply, before the divide. In IR, the difference is:
%5 = mul nsw i32 %4, %tmp1
2010 Jan 22
0
[LLVMdev] Exception handling question
Hi James,
> I've been trying to get a minimal test function to work, which simply
> invokes _Unwind_RaiseException with a single clean-up landing pad.
> However. when I run it my personality function is not getting called -
> _Unwind_RaiseException simply returns apparently doing nothing. Looking
> at the x86-64 assembly output from llc, I can see this is happening
>
2009 Jan 01
1
[LLVMdev] Win32 JIT issue + bug in ScheduleDAGSNodes.h?
Bill Wendling wrote:
> On Dec 31, 2008, at 5:57 AM, srs wrote
>> Bill Wendling wrote:
>>
>>> On Dec 30, 2008, at 4:51 PM, srs wrote:
>>>
>>>
>>>
>>>> 2. There seems to be an issue in ScheduleDAGSDNodes.h when in debug
>>>> mode. The problem is the evaluation of "&SUnits[0];" which