similar to: [LLVMdev] vector optimization

Displaying 20 results from an estimated 600 matches similar to: "[LLVMdev] vector optimization"

2010 May 14
0
[LLVMdev] vector optimization
Instcombine does of this, late codegen also does some of it. -Chris On May 14, 2010, at 5:58 AM, Jochen Wilhelmy <j.wilhelmy at arcor.de> wrote: > Hi! > > Is there a pass that optimizes vector operations? > If I have for examle a sequence of shufflevector instructions > that optimizes them? > (in opencl notation e.g. a.xyzw.wzyx.xxxx -> a.wwww) > > -Jochen
2009 Apr 01
2
[LLVMdev] Shuffle combine
Hi all, I'm having some trouble understanding the following lines in InstructionCombining.cpp, which possibly contain a bug: if (Mask[i] >= 2*e) NewMask.push_back(2*e); else NewMask.push_back(LHSMask[Mask[i]]); When Mask[i] is bigger than the size of LHSMask it reads out of bounds on that last line. I believe the first line is there to try to prevent that but then it
2009 Apr 01
2
[LLVMdev] Shuffle combine
Hi Stefanus, Thanks for the info. I still think it's a bug though. Take for example a case where the vectors each have four elements. The values in Mask[] can range from 0 to 7, while HLSMask only has 4 elements. So LHSMask[Mask[i]] can go out of bounds, no? Cheers, Nicolas From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Stefanus Du
2009 Apr 02
2
[LLVMdev] Shuffle combine
Hi Stefanus, Thanks for verifying this. Could you patch this or should I open a new bug report and find a generic solution first? Cheers, Nicolas From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Stefanus Du Toit Sent: woensdag 1 april 2009 18:59 To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Shuffle combine On 1-Apr-09, at 12:42
2009 Apr 01
0
[LLVMdev] Shuffle combine
Hi Nicolas, On 1-Apr-09, at 7:34 AM, Nicolas Capens wrote: > I’m having some trouble understanding the following lines in > InstructionCombining.cpp, which possibly contain a bug: > > if (Mask[i] >= 2*e) > NewMask.push_back(2*e); > else > NewMask.push_back(LHSMask[Mask[i]]); > > When Mask[i] is bigger than the size of LHSMask it reads out of > bounds
2009 Apr 01
0
[LLVMdev] Shuffle combine
On 1-Apr-09, at 12:42 PM, Nicolas Capens wrote: > Hi Stefanus, > > Thanks for the info. I still think it’s a bug though. Take for > example a case where the vectors each have four elements. The values > in Mask[] can range from 0 to 7, while HLSMask only has 4 elements. > So LHSMask[Mask[i]] can go out of bounds, no? Good point! One easy way to fix this would be to use:
2009 Apr 03
0
[LLVMdev] Shuffle combine
Hi Nicolas, On 2-Apr-09, at 6:04 PM, Nicolas Capens wrote: > Thanks for verifying this. Could you patch this or should I open a > new bug report and find a generic solution first? I don't have write access so the best I could do would be to submit a patch, and I'm crazy busy at the moment. I actually think the check I described below is fine and would fix this bug (but
2005 Aug 29
2
delay before dial on TDM04B - continued
I tried adding wwww to my dial string... It appears to not made any differnece. I see by watching show channels that the w's are there in the dial. I have this box connected to bell south down in georgia. I have an identical box connected in indiana. The box in indiana works fine when dialing out. When in GA dialout is getting "you must first dial a 1 to place this call". show
2007 Feb 05
1
Inserting a pause with Sipura in between
I've a problem with inserting a "pause" and dialing additional numbers when going through Sipura-3000 exten => _12,1,Dial(SIP/4751724@pstn-5,30,D(wwwwww18)) D(wwww) doesn't work as it sends the DTMF tones right after FXS connects to FXO; though, I want insert a "pause" and send additional numbers after connection goes through FXO. Is it possible? -- #Joseph
2013 Oct 04
1
[Bug 70130] New: unable to compile fragment shader program
https://bugs.freedesktop.org/show_bug.cgi?id=70130 Priority: medium Bug ID: 70130 Assignee: nouveau at lists.freedesktop.org Summary: unable to compile fragment shader program Severity: normal Classification: Unclassified OS: Linux (All) Reporter: infyquest at gmail.com Hardware: x86 (IA32)
2011 Jun 25
1
Regression: sockets for 3.0.9pre1 ?
Hi. rsync 3.0.8 FreeBSD RELENG_4 i386. rsync -Haxi --delete /.../ /.../ The first pathspec above (residing on zz, a full filesystem) is: /vvvv/wwww/xxxx/zz/ The second pathspec above (residing on yyy, an empty filesystem) is: /vvvv/wwww/xxxx/yyy/zz/ It's obviously a 'copy everything over' operation. I've had to obfuscate the pathnames, however the exact pathlength throughout
2010 Oct 04
2
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG
Bill Wendling wrote: > On Sep 30, 2010, at 2:13 AM, Heikki Kultala wrote: > >> Bill Wendling wrote: >>> On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: >>> >>>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>> >>>>> I've
2005 Jun 07
5
redirect and special rules
Hi! REDIRECT lan 3328 tcp www - !192.168.0.0/29,10.0.0.0/16 This rules redirect all traffic web to proxy but howto exclude 1 ip from redirect ?? REDIRECT lan 53 tcp domain - REDIRECT lan 53 udp domain - And in this case howto exclude some ip ? Thx.
2012 May 01
0
Regarding SR Reattchemnet in XCP 1.5
I created a NFS VHD SR(\nfs\xxxx-yyyy-zzzz-wwww) on host “A” and created set of disks(vhds). I de-attached the SR from “A” and attached to host “B”. Host B seeing all the disks. Its working up to that fine. But I again de-attached the SR and attached to host A, it shows no disks in that SR. While reattaching to host “A” it shows the SR existing but after attached nothing comes. If I create
2015 Dec 22
2
Question about TargetLowering::SimplifyDemandedBits with AND
Hi All, I have faced a problem with TargetLowering::SimplifyDemandedBits with AND. Here is a example as following: /* C source code */ struct A { unsigned int a; unsigned char c1, c2; bool b1 : 1; bool b2 : 1; bool b3 : 1; }; int main () { struct A x[1]; x[0].b1 = false; int s = 0; s = x[0].b1 ? 1 : 0; <--- Here is problem. if (s != 0) __builtin_abort
2010 Feb 02
1
[LLVMdev] llvm::ShuffleVectorInst yields incorrect vector length in 2.6
Bob Wilson-3 wrote: > >> >> %13 = load <3 x float>* %w ; <<3 x float>> >> [#uses=0] >> %14 = shufflevector <3 x float> %13, <3 x float> undef, <2 x i32> <i32 >> 1, >> i32 0> ; <<3 x float>> [#uses=0] > > The type of %14 should be <2 x float>, since the elements are
2019 Jan 31
4
[RFC] Vector Predication
Philip Reames <listmail at philipreames.com> writes: > Question 1 - Why do we need separate mask and lengths? Can't the > length be easily folded into the mask operand? > > e.g. newmask = (<4 x i1>)((i4)%y & (1 << %L -1)) > and then pattern matched in the backend if needed I'm a little concerned about how difficult it will be to maintain enough
2016 Jun 03
13
[Bug 96355] New: Performance: extra&costly SSBO validation even when SSBO aren't used
https://bugs.freedesktop.org/show_bug.cgi?id=96355 Bug ID: 96355 Summary: Performance: extra&costly SSBO validation even when SSBO aren't used Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component:
2018 Sep 04
2
LoopVectorizer: shufflevectors
Hi, I have been discussing a bit with Sanjay on how to handle the poor sequences of shufflevector instructions produced by the loop vectorizer and he suggested we bring this up on llvm-dev. I have run into this in the past also and it surprised me to again see (on SystemZ) that the vectorized loop did many seemingly unnecessary shuffles. In this case (see
2010 Feb 02
0
[LLVMdev] llvm::ShuffleVectorInst yields incorrect vector length in 2.6
On Feb 2, 2010, at 4:56 AM, Maarten Hoeben wrote: > > Hi, > > When I emit the llvm::ShuffleVectorInst instruction from my code generator > the result vector has the length of vector 1, instead of the element type of > vector 1 and the length of the mask vector; > > %13 = load <3 x float>* %w ; <<3 x float>> [#uses=0] > %14 =