Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] Register allocation questions"
2010 Aug 16
0
[LLVMdev] NumLoads/NumStores for linearscan?
On Aug 15, 2010, at 5:12 PM, Silvio Ricardo Cordeiro wrote:
> Is there a way for me to collect statistics about the number of loads/stores added by the "linearscan" register allocator (just like can be done with the "local" allocator)? I still haven't grokked very well the interaction between RALinScan and Spiller... Should I add those two statistics to the
2011 Jan 21
2
[LLVMdev] [LLVMDev] Reg Alloc: Spiller::Spill question
Spiller::Spill( LiveInterval *li,
SmallVectorImpl<LiveInterval*> &newIntervals,
const SmallVectorImpl<LiveInterval*> &spillIs );
has two reference vectors which contain a small list of Live Intervals. What
is the register allocator's job to do with these intervals other than
analysis. What more needed other than to know
2011 Jan 21
0
[LLVMdev] [LLVMDev] Reg Alloc: Spiller::Spill question
Jeff Kunkel <jdkunk3 at gmail.com> writes:
> Spiller::Spill( LiveInterval *li,
> SmallVectorImpl<LiveInterval*> &newIntervals,
> const SmallVectorImpl<LiveInterval*> &spillIs );
>
> has two reference vectors which contain a small list of Live
> Intervals. What is the register allocator's job to do
2010 Aug 16
2
[LLVMdev] NumLoads/NumStores for linearscan?
Hi,
Is there a way for me to collect statistics about the number of loads/stores
added by the "linearscan" register allocator (just like can be done with the
"local" allocator)? I still haven't grokked very well the interaction
between RALinScan and Spiller... Should I add those two statistics to the
spiller's class?
Thanks,
-- Silvio Ricardo Cordeiro
--------------
2007 Aug 07
0
[LLVMdev] Spillers
On 8/7/07, David Greene <dag at cray.com> wrote:
>
> On Monday 06 August 2007 12:15, Anton Vayvod wrote:
>
> > Spill intervals must be precolored because they can't be spilled once
> more.
> > They are the shortest intervals precisely over each def/use of the
> original
> > interval. That is why they also have their weights set to #INF.
>
> Yes,
2010 Aug 24
2
[LLVMdev] NumLoads/NumStores for linearscan?
On Sun, Aug 15, 2010 at 10:04 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote:
>
> On Aug 15, 2010, at 5:12 PM, Silvio Ricardo Cordeiro wrote:
>
> > Is there a way for me to collect statistics about the number of
> loads/stores added by the "linearscan" register allocator (just like can be
> done with the "local" allocator)? I still haven't
2009 Feb 27
2
[LLVMdev] Easiest way to rewrite machine instructions when each live range of a LiveInterval may be assigned a different physical register
Hi,
I'm working on the implementation of Extended Linear Scan register
allocator as described by Sarkar & Bodik.
One of the interesting features of their algorithm is the possibility
to allocate different physical registers to different live-ranges of
the same LiveInterval. Of course, it may require some glue code to be
inserted in cases, where different physical regs were assigned to
2009 Jan 30
1
[LLVMdev] Question about VNInfo updates by LiveIntervals::addIntervalsForSpills
Hi,
It looks like LiveIntervals::addIntervalsForSpills does not update all
of the LiveIntervals infos quite correctly.
In particular, if a live interval L is defined by Reg<-Reg copy
instructions whose srcReg is later spilled by the
addIntervalsForSpills() function, its VNInfo information is not
updated in a proper way. It still points to the same MachineInstr as
before, even though the
2007 Aug 06
5
[LLVMdev] Spillers
Can someone explain the theory behind the spillers in VirtRegMap.cpp?
It seems as though the spillers do triple duty:
- Insert load/store operations and/or fold instructions as necessary to carry
out spills
- Rewrite the spilled virtual registers to use machine registers (mapping
given by the caller in the VRM).
- Rewrite machine code to change virtual registers to physical registers
2009 Feb 27
0
[LLVMdev] Easiest way to rewrite machine instructions when each live range of a LiveInterval may be assigned a different physical register
On Feb 27, 2009, at 7:20 AM, Roman Levenstein wrote:
> Hi,
>
> I'm working on the implementation of Extended Linear Scan register
> allocator as described by Sarkar & Bodik.
> One of the interesting features of their algorithm is the possibility
> to allocate different physical registers to different live-ranges of
> the same LiveInterval. Of course, it may require
2008 Jan 23
2
[LLVMdev] LiveInterval Splitting & SubRegisters
On Wednesday 23 January 2008 02:01, Evan Cheng wrote:
> On Jan 22, 2008, at 12:23 PM, David Greene wrote:
> > Evan,
> >
> > Can you explain the basic mechanics of the live interval splitting
> > code?
> > Is it all in LiveIntervalAnalysis.cpp under addIntervalsForSpills
> > and child
> > routines? What is it trying to do?
>
> It's splitting
2009 Feb 28
1
[LLVMdev] Easiest way to rewrite machine instructions when each live range of a LiveInterval may be assigned a different physical register
Hi Evan,
Thanks a lot for your reply!
2009/2/27 Evan Cheng <evan.cheng at apple.com>:
>
> On Feb 27, 2009, at 7:20 AM, Roman Levenstein wrote:
>
>> Hi,
>>
>> I'm working on the implementation of Extended Linear Scan register
>> allocator as described by Sarkar & Bodik.
>> One of the interesting features of their algorithm is the possibility
2008 Feb 15
2
[LLVMdev] LiveInterval spilling (was LiveInterval Splitting & SubRegisters)
Hi Evan,
I have a few questions about current implementation of live intervals
spilling, which is required for the implementation of Extended Linear
Scan algorithm.
--- Evan Cheng <evan.cheng at apple.com> wrote:
> > On Wednesday 23 January 2008 02:01, Evan Cheng wrote:
> >> On Jan 22, 2008, at 12:23 PM, David Greene wrote:
> >>> Evan,
> >>>
>
2007 Aug 06
4
[LLVMdev] Spillers
On Monday 06 August 2007 12:15, Anton Vayvod wrote:
> Spill intervals must be precolored because they can't be spilled once more.
> They are the shortest intervals precisely over each def/use of the original
> interval. That is why they also have their weights set to #INF.
Yes, that's true. But I wonder if we shouldn't be smarter about which
register we pick to color it.
2008 Jan 25
0
[LLVMdev] LiveInterval Splitting & SubRegisters
On Jan 23, 2008, at 2:40 PM, David Greene <dag at cray.com> wrote:
> On Wednesday 23 January 2008 02:01, Evan Cheng wrote:
>> On Jan 22, 2008, at 12:23 PM, David Greene wrote:
>>> Evan,
>>>
>>> Can you explain the basic mechanics of the live interval splitting
>>> code?
>>> Is it all in LiveIntervalAnalysis.cpp under
2008 Jan 22
4
[LLVMdev] LiveInterval Splitting & SubRegisters
Evan,
Can you explain the basic mechanics of the live interval splitting code?
Is it all in LiveIntervalAnalysis.cpp under addIntervalsForSpills and child
routines? What is it trying to do?
Also, in the ancient subregister coalescing code, there used to be an update
of the SSARegMap to point subregisters to the superregister they were
coalesced to (IIRC). That has since gone away. I used to
2007 Aug 07
0
[LLVMdev] Spillers
Hi,
Sorry for the delay. I was trying to wrap my head around some live
interval analysis code and have forgotten about emails. :-)
On Aug 6, 2007, at 9:20 AM, David Greene wrote:
> Can someone explain the theory behind the spillers in VirtRegMap.cpp?
>
> It seems as though the spillers do triple duty:
>
> - Insert load/store operations and/or fold instructions as
>
2008 Jan 23
0
[LLVMdev] LiveInterval Splitting & SubRegisters
On Jan 22, 2008, at 12:23 PM, David Greene wrote:
> Evan,
>
> Can you explain the basic mechanics of the live interval splitting
> code?
> Is it all in LiveIntervalAnalysis.cpp under addIntervalsForSpills
> and child
> routines? What is it trying to do?
It's splitting live intervals that span multiple basic blocks. That
is, when an interval is spilled, it
2008 Feb 15
0
[LLVMdev] LiveInterval spilling (was LiveInterval Splitting & SubRegisters)
Hi, Roman,
maybe I can try to answer this. I think that all boils down to having
register to reload spilled values. Once a register is spilled, its live
range is split into smaller pieces. These pieces most be contained into
registers, and it is the task of the allocator to find these registers.
Imagine that you have something like:
Before After
allocation: allocation:
a
2007 Aug 07
2
[LLVMdev] Spillers
On Tuesday 07 August 2007 05:00, Anton Vayvod wrote:
> > Yes, that's true. But I wonder if we shouldn't be smarter about which
> > register we pick to color it. In Bill W's implementation, it was
> > essentially random. What was your solution to this?
>
> I allocated spill intervals at the beginning of each iteration so all the
> rest intervals (except of