similar to: [LLVMdev] LLVM on ARM with the EABI

Hello llvm'ers, We are using the llvm compiler tools (llvm-link, llc, etc) to generate code for ARM for the Android NDK. We're on a pretty tight deadline and have a host of issues that we could use some help overcoming. We're interested in bringing on a contractor experienced in llvm to help us. Broadly, llc is giving various assertion failures while generating the native code

Hi list, For a tool I'm working on I'd like to know where instructions end up in compiled executables by looking them up in the symbol table. Therefore, I've been trying to use the llvm.pcmarker Intrinsic, but I've had no luck. When I pass .bc files with this intrinsic into llc, I'm given this error: LLVM ERROR: Cannot yet select: 0x2026938: ch PCMarker 0x1f0c678, 0x20268b0

Hi, I was comparing the way LLVM generates the exception table and it looks a bit different from what GCC (arm-none-eabi-g++) generates. Maybe that's because clang is not generating ARM IR when I do: $ clang -c -emit-llvm -march=arm -mcpu=cortex-a8 -mtriple=arm-none-eabi exception.cpp -o exception.clang.bc clang: warning: argument unused during compilation: '-mcpu=cortex-a8' clang:

On 18 April 2016 at 16:18, Silviu Baranga <Silviu.Baranga at arm.com> wrote: > This doesn't look like something ACLE specific (I can't find it in the ACLE doc). Sorry, I didn't mean it was ACLE, only that you guys were fiddling with macros. :) > This seems to be a generic macro. I think it would make sense to define it > if we know we're emitting ELF. Since the

On 18 April 2016 at 16:33, Silviu Baranga <Silviu.Baranga at arm.com> wrote: > Doing a grep "eabi" * -R | grep darwin in llvm I found the test divmod-eabi.ll > which uses the triple armv7-apple-darwin-eabi. What format does that have? Certainly not ELF. :) But I didn't mean "has eabi on triple", but "is in none-eabi mode", which may have to check a

I'm facing a problem with functions arguments. ARM EABI defines that 8-bytes arguments must be 8-bytes aligned. For example: void @f(i32 %a, i64 %b) ARM EABI: r0 <- %a r2,r3 <- %b Darwin: r0 <- %a r1,r2 <- %b void @g(i32 %a, i32 %b, i32 %c) ARM EABI or Darwin: r0 <- %a r1 <- %b r2 <- %c The problem is: I can't differ a i64 argument of two i32 arguments in

Attached is a port of the new ARM eabi from gcc 4.1 to the llvm-gcc branch. With this patch I am able to bootstrap the 4.0 branch using the new eabi. The llvm-gcc branch fails with ------------------------------------ internal compiler error: in prune_unused_types_update_strings, at dwarf2out.c:14372 ------------------------------------ But I believe that this is an unrelated problem and I will

On Mon, Dec 09, 2013 at 01:58:29PM +0000, Renato Golin wrote: > I can see the error, and it's just a bad selection of choices. I was > wrong in assuming that the "eabi" at the end would always force it: > > $ clang -target arm-elf-eabi -S mod.c -o - | grep mod > .file "mod.c" > bl __modsi3 > bl __umodsi3 I was discussing this with Tim on IRC and he

On Feb 8, 2007, at 10:46 AM, Lauro Ramos Venancio wrote: > I'm facing a problem with functions arguments. ARM EABI defines that > 8-bytes arguments must be 8-bytes aligned. For example: > > void @f(i32 %a, i64 %b) > > ARM EABI: > r0 <- %a > r2,r3 <- %b Ok. I suppose this makes it easier to use 64 bit store instructions. > > Darwin: > r0 <- %a >

Hi all, I am trying to cross-compile my application for ARM Cortex-M3. Here's how I'm doing it: 1, Get a pre-built GNU toolchain for ARM Cortex-M processors from https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads 2, Create an object file for ARM: clang -c -target arm-none-eabi -mcpu=cortex-m3 -mthumb -O3 -g

I am new to LLVM but have perused the code alongside using llvm-gcc and CLANG to build ARM EABI objects. Based on this superficial analysis it appears that LLVM currently does not support the ARM Exception Handling ABI (as defined under the EABI). Can anyone comment on whether plans are in place to remedy this? I did see the discussion regarding work on the MC for ARM. Will this work include

On 9 December 2013 11:51, Joerg Sonnenberger <joerg at britannica.bec.de> wrote: > Part of the concern is that the same code using / does call __aeabi_idiv > and __aeabi_uidiv. Hi Joerg, I can see the error, and it's just a bad selection of choices. I was wrong in assuming that the "eabi" at the end would always force it: $ clang -target arm-elf-eabi -S mod.c -o - |

> -----Original Message----- > From: Anton Korobeynikov [mailto:anton at korobeynikov.info] > > Neither llvm-gcc nor clang support exceptions on ARM (except, maybe, > sjlj excheptions on arm/darwin). I have some patched uncommitted for > EH on ARM but they are too far from being complete. Hi Anton, Are you actively working in that area? I did some experiments and managed to

> > Yes, you need to override both LowerArguments and LowerCallTo. All of > the current targets / abi's use the default implementation in > SelectionDAGISel.cpp But I guess ARM EABI will be the first. :-) As > far as I can see, this is the only clean way to do it. I expect the > ARM EABI specific implementation will be quite a bit simpler than the > default implementation

On 16 April 2016 at 01:44, Zhao, Weiming via cfe-dev <cfe-dev at lists.llvm.org> wrote: > I'm building libunwind for ARM baremetal using clang. > I notice that __ELF__ is used in libunwind and the macro is only defined for > Linux target on ARM. > Should we also predefine that for arm-none-eabi target? Do you mean in Clang's ARMTargetInfo::getTargetDefines() ? I think

On Mon, Sep 27, 2010 at 8:50 AM, Dennis Taul <dtaul at codeaurora.org> wrote: > > I am new to LLVM but have perused the code alongside using llvm-gcc > and CLANG to build ARM EABI objects. > > Based on this superficial analysis it appears that LLVM currently does > not support the ARM Exception Handling ABI (as defined under the > EABI). > > Can anyone comment on

On Mon, Dec 09, 2013 at 07:56:26AM +0000, Tim Northover wrote: > Hi Joerg, > > > At the moment, this will call __modsi3 and __umodsi3, even though those > > functions are not part of AAPCS. Should this be considered a lowering > > bug in the ARM target? > > LLVM actually supports both variants, depending on the target. The > __aeabi_* functions are part of the

Yes, I see the load is 8-byte aligned in the bit code. My question was, assuming that arguments requiring double word alignment have to be passed in even/odd registers, how does the backend know that %0 has to be passed in register r2 and r3? *tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwindt * It doesn't seem that ARM backend can figure out that "[2 x i32]

The buildbot @ http://lab.llvm.org:8011/builders/llvm-gcc-i686-pc-linux-gnu-cross-arm-eabi-soft-float/builds/850 is failing with following assertion failure. Is it possible for someone to collect a preprocessed source file and file a PR ? Thanks, - Devang cc1: /opt/buildslave/osuosl/slave/llvm-gcc-i686-pc-linux-gnu-cross-arm-eabi-soft-float/llvm.src/lib/CodeGen/LiveIntervalAnalysis.cpp:713: bool

See ARMCallingConv.td:113. The alignment of the arg is checked and if it's 8-byte aligned, the proper registers are chosen. deep On Tue, Aug 7, 2012 at 1:20 AM, Akira Hatanaka <ahatanak at gmail.com> wrote: > Yes, I see the load is 8-byte aligned in the bit code. > > My question was, assuming that arguments requiring double word alignment > have to be passed in even/odd