similar to: [LLVMdev] how to set -pre-ra-sched from code?

Sanjiv Gupta wrote: > On Wed, 2010-04-14 at 11:33 -0400, Andrew Friedley wrote: >> I've found that I need to set the -pre-RA-sched parameter when using >> tools like llc to get the kind of instruction scheduling I want. >> >> However I'm normally generating and running code on the fly using the >> JIT, and can't figure out how to set the -pre-RA-sched

Sorry for responding to my own message but I would really appreciate some help with this. Looking through the documentation again this morning I noticed that setSchedulingPreference is a protected method of LLVMTargetLowering, so it looks like it's not something I can call directly anyway. Furthermore it's only called from one place with a hard-coded value for any particular

On Wed, 2010-04-14 at 11:33 -0400, Andrew Friedley wrote: > I've found that I need to set the -pre-RA-sched parameter when using > tools like llc to get the kind of instruction scheduling I want. > > However I'm normally generating and running code on the fly using the > JIT, and can't figure out how to set the -pre-RA-sched option anywhere > other than on the

Hi Andrew, On 04/19/10 14:27, Andrew Friedley wrote: > Sorry for responding to my own message but I would really appreciate > some help with this. > > Looking through the documentation again this morning I noticed that > setSchedulingPreference is a protected method of LLVMTargetLowering, so > it looks like it's not something I can call directly anyway. > Furthermore

Hi, LLVM, I found LLVM codegen has 3 passes for instruction scheduling: 1) pre-ra sched 2) post-ra sched 3) mi sched. for RISC machines, there are data hazard cases appear only after Register Allocation(RA). for example, $t0 is used immediately after writing(RAW): ld $t0, MEM add $t2, $t0, $0 There may be one or more stall in pipeline. Instruction scheduler can detect this kinds of conflict

Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so you will have to compile with -O3. You can also invoke the MI (pre-RA) scheduler with llc option "-enable-misched". As you have pointed out, the post-isel scheduler is mandatory, and therefore you don't have to give any command line options. Currently, mips has only one generic scheduling itinerary model in

Hi, Akira, I found you maintain mips MipsSchedule.td. does it correct? in MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no ByPass info out there. are you sure this reflects the real R4xxx/R5xxx processors. why IILoad uses funcition unit ALU? InstrItinData<IILoad , [InstrStage<3, [ALU]>]> for my previous question, I have new input after

Akira, Thanks you for response. I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But I found mips codes are good enough by default. basically, I can not easily eyeball any bubbles. I don't understand how they can do that without post-RA-sched. pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little information and they can only schedule node in topology

hi, LLVM, I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as physical register data hazard. Is it useful to optimize processor pipeline? thanks, --lx

On Sep 21, 2013, at 8:02 PM, Liu Xin <navy.xliu at gmail.com> wrote: > hi, LLVM, > > I found there is a flag DisableHazardRecognizer in TargetInstrImpl.cpp. I still don't understand how llvm detects data hazard in pre-RA-sched. pre-RA-sched is based on SDNode and all operands are vregs. Even you can calculate the operators of SDNodes, the data hazard in vreg are not same as

On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Andrew, > > Thank you for answering my question. > > What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems

Hi, Andrew, Thank you for answering my question. What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems that you want to balance register pressure and ILP in misched. On Tue, Sep 24, 2013 at 4:07 PM,

On Sep 25, 2013, at 11:03 PM, Liu Xin <navy.xliu at gmail.com> wrote: > > > > On Wed, Sep 25, 2013 at 1:15 PM, Andrew Trick <atrick at apple.com> wrote: > > On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > >> Hi, Andrew, >> >> Thank you for answering my question. >> >> What's the status of

On Wed, Sep 25, 2013 at 1:15 PM, Andrew Trick <atrick at apple.com> wrote: > > On Sep 24, 2013, at 7:59 PM, Liu Xin <navy.xliu at gmail.com> wrote: > > Hi, Andrew, > > Thank you for answering my question. > > What's the status of misched? is it experimental? I found it is disabled > by default for all architectures(3.4svn). I also don't understand

On Fri, Sep 20, 2013 at 3:30 AM, Liu Xin <navy.xliu at gmail.com> wrote: > Hi, Akira, > > I found you maintain mips MipsSchedule.td. does it correct? in > MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no > ByPass info out there. > are you sure this reflects the real R4xxx/R5xxx processors. > > why IILoad uses funcition unit ALU? >

> I'll be happy to answer any further questions you may have, feel free to e-mail > me directly (though right now our mail server is down) > The salient features that we want to have in the driver are: 1. llvm-ld will be used as "The Optimizer". 2. If the user has specified to generate the final executable, then llvm-ld should run on all the .bc files generated by clang

While looking at why some generated code for SPARC was poor, I ran into the fact that the MachineScheduler is not yet enabled by default -- it's opt in for each target. Having a bunch of deprecatedish code around was a bit confusing for newbie me. So, I suggested on IRC that perhaps it's been long enough by now that any target that hasn't switched over probably isn't actually

Hi Sanjiv, Sanjiv Gupta <sanjiv.gupta <at> microchip.com> writes: > The salient features that we want to have in the driver are: > [...] As promised, I've implemented a basic compiler driver for the PIC16 toolchain. It's under tools/llvmc/examples/mcc16. Some examples illustrating the features you requested: > 2. If the user has specified to generate the final

PIC16 now has clang and llc based system to generate native assembly. We then use our native assembler (gpasm) and the native linker (mplink) to generate the final executable. How can I integrate these things with the driver llvmc to have gcc like user experience? Note that we also want to run llvm-ld in order to perform the LTOs in case of multiple files. - Sanjiv

Mikhail Glushenkov wrote: > > Hi Sanjiv, > > Sanjiv Gupta <sanjiv.gupta <at> microchip.com> writes: > > > The salient features that we want to have in the driver are: > > [...] > > As promised, I've implemented a basic compiler driver for the > PIC16 toolchain. It's under tools/llvmc/examples/mcc16. > Hi Mikhail, How do you build mcc16