similar to: [LLVMdev] How to specify the subtarget instruction set for LLVM unit in ARM-backend?

Dear developers! I’d like to ask you a question concerning the implementation of one algorithm for the generation of energy-efficient code for ARM processors. Unfortunately, the documentation on this subject is incomplete on your site, so could you please explain how to implement my algorithm. Without going into details, I would like to say, that the implementation of this algorithm

Dear developers! I have one problem and two options for its solution: • I can make a simple pass which will specify the subtarget instruction set (ARM or Thumb) for a particular instruction (or a basic block) LLVM intermediate representation OR • I can add a special pass to arm backend which will do the same (specify subtarget instruction set (ARM or Thumb) for a particular

I am working on an LLVM backend for the AVR architecture, and am having troubles working with the codegen layer, trying to get around the quirks of the binary encodings of the AVR ISR. There are several different families of AVR microcontrollers, each with a minimum 'core' instruction set. Each family builds upon (or removes) the core ISR with more instructions or different encodings. My

Hi all, I've just filed PR12794: Add ARM cpu / subtarget features auto-detection. And I would very much appreciate the community's help to implement this. What motivated this? Well this: http://www.phoronix.com/scan.php?page=news_item&px=MTA5OTM I believe one of the reason the benchmark numbers are totally bogus is that the compilation are done on ARM hosts. Given the benchmarks are

Hi all, I have a sample test case : $ cat 1.c int foo(int x, int y){ int z = x + y; return z/2; } I tried to get its IR form with clang providing subtarget feature as mmx for target x86_64 $ clang -O3 -mmmx 1.c -S -emit-llvm in the IR generated i can see the subtarget-features as function attribute : "target-features"="+mmx" In the SelectionDAG phase in file

> I've just filed PR12794: Add ARM cpu / subtarget features auto-detection. And I would very much appreciate the community's help to implement this. > > What motivated this? Well this: > http://www.phoronix.com/scan.php?page=news_item&px=MTA5OTM > > I believe one of the reason the benchmark numbers are totally bogus is that the compilation are done on ARM hosts.

Hi, I found some different discrepancy on how Subtarget is created between some arch specific TargetMachine constructor. For example, for BPF/Lanai: BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options,

[resending to correct llvm-dev address] Hi, I’d like to start enabling the loop data prefetch pass for Cyclone (an ARM64 subtarget). AFAICT, you can’t really add passes specifically to a subtarget but only to a target. This makes sense because in the new world, you could have different subtargets per function. I just want to make sure my understanding is correct. My plan is to add the pass

On 11/05/12 04:56, 陳韋任 wrote: >> I've just filed PR12794: Add ARM cpu / subtarget features auto-detection. And I would very much appreciate the community's help to implement this. >> >> What motivated this? Well this: >> http://www.phoronix.com/scan.php?page=news_item&px=MTA5OTM >> >> I believe one of the reason the benchmark numbers are totally

Hi, while implementing SystemZTTI:getCacheSize(), it became clear that there really isn't a simple way to just ask the Subtarget for the current subtarget machine model. I was thinking like something of an enum that would also reflect the subtarget series (and would allow >= and similar operations). I would like to ask what the ideas are on how this should be done best. Some

If you want to create a version for the mips1 subtarget, going back in time will probably be a lot of work for you. If you want to modify the current version you might try the following: 1) Create a Mips1 predicate and use that to disable instruction patterns that match using non Mips1 instructions. 2) Use soft-float 3) You would need to reenable some commented out code used to implement

On May 11, 2012, at 12:25 AM, James Molloy wrote: > On 11/05/12 04:56, 陳韋任 wrote: >>> I've just filed PR12794: Add ARM cpu / subtarget features auto-detection. And I would very much appreciate the community's help to implement this. >>> >>> What motivated this? Well this: >>> http://www.phoronix.com/scan.php?page=news_item&px=MTA5OTM

Thanks, Alex. See my comments below. On Wed, Aug 23, 2017 at 12:59 AM, Alex Bradbury <asb at asbradbury.org> wrote: > On 22 August 2017 at 23:39, Y Song via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> Hi, > > Hi Yonghong. > >> I found some different discrepancy on how Subtarget is created >> between some arch specific TargetMachine constructor.

Hello, I'm implementing a port of LLVM for PowerPC VLE. It's a compressed instruction set similar to mips16 and ARM Thumb. Instruction encoding (VLE/non-vle) is selected for a given memory region by an attribute in a memory area descriptor. Targets supporting this that I know of are all bare-metal (so powerpc-none-elf). I'm trying to implement ELF support right now. VLE ELF files

My guess is he wants mips1 so that he doesn't have to worry about the patented mips instructions? At any rate, it will be a bit of work to enable a mips1 target and I doubt many people are interested, so it'll definitely be up to him to do the work. -eric On Fri, Apr 26, 2013 at 10:15 AM, Reed Kotler <rkotler at mips.com> wrote: > If you want to create a version for the mips1

Hello, I have a compiler in LLVM 2.9 for the KCPM3 processor. I'd like to create a subtarget for the new cpu version called KCPSM6. Besides a couple of new instructions which are not important at the moment, the KCPSM6 cpu has different instruction opcodes. Semantically the instructions are the same, hence I'd like to keep all the lowering and pattern matching stuff unmodified For

Thanks Kevin for the reply. I got the point now :) On 10 Apr 2015 00:18, "Smith, Kevin B" <kevin.b.smith at intel.com> wrote: > For x86_64 ABI, a minimum feature set of SSE2 is required. > > > > Kevin > > > > *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On > Behalf Of *suyog sarda > *Sent:* Thursday, April 09,

----- Original Message ----- > From: "Bill Schmidt" <wschmidt at linux.vnet.ibm.com> > To: llvmdev at cs.uiuc.edu > Sent: Thursday, January 31, 2013 9:26:15 AM > Subject: [LLVMdev] Getting command line options to affect subtarget features > > The problem I'm trying to solve: Invoking clang on PowerPC with > -fno-altivec has no effect. > > From what

Updated patch is attached. Note this is just a work-in-progress patch and I plan to address the feedback comments later if this patch is in the right direction. This is how the command line options are parsed and used by the backend passes: 1. Tools such as clang and llc call cl::ParseCommandLineOptions. Any of the options that should be written to the bitcode as function or module attributes

Is it possible to assign the value of subtarget features using more complex expressions with code as opposed to using the mechanism that tablegen affords. For example, if Mips16 or Micro Mips is not present, then I want the subfeature "standard encoding". If I can't do this, then it requires me to write a more complex expression for the "standard encoding" expresions.