similar to: [LLVMdev] PTX target for LLVM?

On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: > Hi > > I am interested to know: are there are any LLVM targets in the works > for Nvidia's PTX ISA? > > Also if anyone knows about Ocelot (a project done by some students at > my school): it does the opposite of what I am trying to do (translates > PTX to LLVM IR to run Cuda kernels on the CPU). I don't know of

To the list:<br /> <br /> Tons of LLVM research is being done that is damn near worthless to anyone but the person who did it because the team doesn't publish supporting code or even describe at a high level description of the algorithms they're using. And the excuse is always, ALWAYS the same: "we need to clean up the code before we release it."<br /> <br

Hi, (Disabling lurk mode) I must admit, I believe this would be an extremely valuable addition to llvm, to the point where I was also seriously considering writing this backend. The main thing holding me back is the thought that other people are almost certainly working on the same thing (probably including nvidia)! I assume it's not yet ready to publish, but it's worth

Is this the configuration you would give for an iphone? -Puyan ----- Original Message ----- From: "Jim Grosbach" <grosbach at apple.com> To: "Puyan Lotfi" <puyan at gatech.edu> Cc: llvmdev at cs.uiuc.edu Sent: Wednesday, February 17, 2010 4:42:37 PM GMT -05:00 US/Canada Eastern Subject: Re: [LLVMdev] Need help getting LLVM JIT running on ARM Specifying --host,

Puyan, There is a doc on the document page which describe the list of broken GCCs. You'll need to check it once the docs are online. Rajika On Sun, Feb 21, 2010 at 11:33 AM, Puyan Lotfi <puyan at gatech.edu> wrote: > Hi > > Does there exist a list of relative compile times for source files in LLVM? > I am doing a build for ARM on an actual ARM device, and >

>From a cached version of the Getting Started Guide, I have found: "GCC 3.4.4 (CodeSourcery ARM 2005q3-2): this compiler miscompiles LLVM when building with optimizations enabled. It appears to work with "make ENABLE_OPTIMIZED=1 OPTIMIZE_OPTION=-O1" or build a debug build." I'm trying that now. -Puyan On Sun, Feb 21, 2010 at 1:22 AM, Rajika Kumarasiri <rajika at

Specifying --host, --build and --target should work. For example, $ configure --host=arm-apple-darwin10 --build=i686-apple-darwin10 --target=arm-apple-darwin10 --enable-targets=arm -Jim On Feb 17, 2010, at 12:26 PM, Puyan Lotfi wrote: > Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? > I want to use the LLVM JIT on ARM for a class

Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? I want to use the LLVM JIT on ARM for a class project this semester. I have built and/or installed a few different gcc arm (arm-linux, and also one that is arm-elf) toolchains, and have had trouble getting LLVM 2.6 to configure and compile using the --host and --build switches of the config. If there

Hi Does there exist a list of relative compile times for source files in LLVM? I am doing a build for ARM on an actual ARM device, and CodeGenDAGPatterns.cpp is taking a really long time to compile (it's been like 20 minutes or more). I don't even get an error. All the files before it compile pretty quickly but this file in particular just won't finish. The version of gcc I have on

Hi, My name is Puyan and I've been exploring ways to improve the state of instruction level diffing using llvm and MIR. Below is a proposal for a new llvm tool meant to address issues encountered when diffing at the machine level. I'm eager to hear the community's feedback. Thanks PL mir-canon: A new tool for canonicalizing MIR for cleaner diffing. Problem Statement and

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >> Hi, >> >> >>

From: Justin Holewinski [mailto:justin.holewinski at gmail.com] Sent: Tuesday, December 13, 2011 9:48 AM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Changes to the PTX calling conventions On Tue, Dec 13, 2011 at 11:25 AM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote: Currently, PTX has its own calling conventions where

Hi, finally we changed the license of the PTX-backend from GPL to BSD(license of llvm). You can get the latest version here: https://sourceforge.net/projects/llvmptxbackend/ It should be compatible to the current llvm svn trunk. (revision 110329, Thu 05 Aug 2010) The backend now uses the address space attribute of LLVM for local, global, ... and constant address space. However the clang frontend

On Tue, 10 Aug 2010 14:21:43 -0500 "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > > > -----Original Message----- > > From: llvmdev-bounces at cs.uiuc.edu > > [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of David A. Greene > > Sent: Tuesday, August 10, 2010 12:05 PM > > To: Helge Rhodin > > Cc: llvmdev at cs.uiuc.edu > >

Hi I am not sure if it is possible to do something similar to what the LLVM pass framework offers (via the opt program) but in the JIT instead (when running lli). Is it possible to do any kind of online profiling (or optimization) of dynamically compiler code similar to writing an opt style code pass module? Or would I have to change a lot of stuff in the JIT? Thanks -Puyan

Helge Rhodin <helge.rhodin at alice-dsl.net> writes: >> But I didn't study their code thoroughly, so I might be wrong about this. >> > Yes, we don't use the target-independent code generator and the > backend is based on the CBackend. We decided to not use the code > generator because PTX code is also an intermediate language. The > graphics driver

> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of David A. Greene > Sent: Tuesday, August 10, 2010 12:05 PM > To: Helge Rhodin > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] PTX backend, BSD license > > Helge Rhodin <helge.rhodin at alice-dsl.net> writes: > > >> But I

On Tue, Dec 13, 2011 at 12:54 PM, Villmow, Micah <Micah.Villmow at amd.com>wrote: > ** ** > > ** ** > > *From:* Justin Holewinski [mailto:justin.holewinski at gmail.com] > *Sent:* Tuesday, December 13, 2011 9:48 AM > *To:* Villmow, Micah > *Cc:* LLVM Developers Mailing List > *Subject:* Re: [LLVMdev] Changes to the PTX calling conventions**** > > ** ** >

When we discussed this our line of thought was like this: - LLVM IR already uses %name for SSA values which is closer to what a vreg is than to what a physreg is. It would be neat to draw that parallel to llvm IR. - We wanted another sigil for physregs so they are easy to differentiate from vregs to allow people to differentiate vregs/physregs even if they don't know all the physreg names of

Hi Marcello, On Fri, Oct 19, 2012 at 04:38:29PM +0100, Marcello Maggioni wrote: > Hello, > I'm working on a compiler based on LLVM for a SIMD architecture that > supports instruction predication. We would like to implement branching > on this architecture using predication. > As you know the LLVM-IR doesn't support instruction predication, so I'm > not exactly