similar to: [LLVMdev] register aliasing

Hi As part of a requirement that I have, I would like to have some globals reside in registers always. So these variables would not have a home location in memory. I realize the code generated would also need to be aware of this. I do have some ideas on how to change the code appropriately. But right now, I am more concerned about how to fit this requirement (sort of interprocedural) into the

Hi I am running into bunch of windows build issues. Can someone please provide help on what might be going wrong llvm\win32\Configure\..\llvm\ADT\hash_set.h 1>The system cannot find the file specified. Similarly 2>c1xx : fatal error C1083: Cannot open source file: '..\..\lib\Support\Annotation.cpp': No such file or directory thanks in advance shrey

done http://llvm.org/bugs/show_bug.cgi?id=5331 shrey On Wed, Oct 28, 2009 at 3:29 PM, Óscar Fuentes <ofv at wanadoo.es> wrote: > shreyas krishnan <shreyas76 at gmail.com> writes: > >>     I am running into bunch of windows build issues. Can someone >> please provide help on what might be going wrong >> >> >>

Hi I run into an issue as part of splitting a critical edge during LICM. When a new basic block is created and needs to be added into the dominator tree, the block is already in the dominator tree. I print the dominator tree and I see it is added into the tree as child of node it is supposed to dominate. How do I debug to find out why/when its getting added into the tree. ? Tips/suggestions on

Thanks Eli, Jaffrey for the pointer! A couple of further questions if I may 1. Isnt this assuming that register being pinned to is always esi when it comes to using a calling convention. I would like to pin the register through a pass and so I dont know which registers ends up being used for a particular value before hand 2. I would also like to allocate some small aggregates into registers. I

I tried adding them in my backend however I run into the assertion assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 && ExtType < array_lengthof(LoadExtActions) && "Table isn't big enough!"); What does the assertion mean ? thanks for all help!! shrey On Wed, Jul 14, 2010 at 6:56 PM, Eli Friedman <eli.friedman at

Chris recently wrote up a way to do this at http://nondot.org/sabre/LLVMNotes/GlobalRegisterVariables.txt On Thu, Jul 16, 2009 at 1:53 PM, shreyas krishnan<shreyas76 at gmail.com> wrote: > Hi >   As part of a requirement that I have, I would like to have some > globals reside in registers always. So these variables would not have > a home location in memory. > I realize the

hi I find machine register info carrying the lists of def use for each register - PhysRegUseDefLists[RegNo];. I dont see a lot of places using this. For instance, if this list is accurate, can this be used for def use relationships at different points? thanks shrey

Hi I find types such as v16i32, v16f32 missing in my llvm version 2.7 So does the following page not list them http://llvm.org/docs/doxygen/html/classllvm_1_1MVT.html is that intentional for any reason or can I just add them ? thanks shrey

I am sorry, I actually meant Machine Instructions - is there a way ? One use of that is I would like to be able to group instructions together and be able check their group quickly. thanks shrey On Sun, Aug 14, 2011 at 1:16 AM, Bill Wendling <wendling at apple.com> wrote: > On Aug 13, 2011, at 11:04 AM, shreyas krishnan wrote: > >> Hi >>    Is there a way to associate

Hi all I am building LLVM 2.6 on VC++. I am running into this problem where even builds without any changes whatsoever causes rebuilding of certain directories like table gen of intrinsics and x86 target files. This then leads to build of the x86 codegen. Is this expected ? Any pointers to how I can avoid this? thanks shrey

Hi if I have group of instructions that belong to same basic block, how can I determine which of these occurs the last ? thanks Shrey

Hi I am running into a legalize dag issue after custom lowering a load. If someone can give me pointers that would be great. I am using llvm 2.6 When custom lowering a load, the following code gets executed. Tmp1 = TLI.LowerOperation(Tmp3, DAG); if (Tmp1.getNode()) { Tmp3 = LegalizeOp(Tmp1); Tmp4 = LegalizeOp(Tmp1.getValue(1)); <----------------- what

Hi I would like to add transformation - mostly peephole- after register allocation that make use of def-use information. Would it be possible to make use of the dag codebase to help do that ? thanks for any pointers shrey

thanks for the help ..I do add the chain and the result. My code is like this ... SDValue Ops[] = { load->getChain(), load->getOperand(1), load->getBasePtr(), des }; DAG.getNode(CustomOpc, NodeTys, Ops, 4); thanks again! shrey On Thu, Nov 12, 2009 at 4:41 PM, Anton Korobeynikov <anton at korobeynikov.info> wrote: >> My problem is that the second call asserts inside

HI Is there a public function equivalent of calling getIndex I would like to use some sort of starting slot info of a live interval in some pass. I need a way of comparing which virtual register is associated with an earlier source line without relying on any debug info. The relative order is preserved in my case. thanks shrey

thanks for the help ..I could build it with cmake generated project files Being a newbie with cmake one question, is it equivalent to configure in windows environment and so would need to be run everytime I change the source location ? thanks shrey On Wed, Oct 28, 2009 at 4:31 PM, shreyas krishnan <shreyas76 at gmail.com> wrote: > done > >

Hi A bunch of instructions that I have defined in tablegen files get tagged with unmodeledSideEffect property. I have defined these instructions with no corresponding dag patterns. Is there a way i can avoid this property and say they do not have any side effects thanks shrey

thanks. One question - Isnt it needed for other arithmetic operations such as add etc ? shrey On Fri, Aug 13, 2010 at 10:36 AM, Anton Korobeynikov <anton at korobeynikov.info> wrote: > Hello > >> if needed conversions are generated. So if  I needed to generate >> different instructions for signed/unsigned, is that possible ? > Yes, see e.g.

Hi Is there a way to associate additional info with every opcode like an id either through the td files or when building an instruction ? thanks shrey