similar to: [LLVMdev] is it possible to use gcc vectorizer ?

Hi Kuan-Hsu, > gcc provides auto-vectorization on the tree-ssa framework, and llvm-gcc > uses tree-ssa to generate LLVM IR. > so, is it possible to use gcc vectorizer in LLVM? in theory yes, but you would have to modify the compiler. In llvm-gcc all gcc optimizers are turned off, and this includes the vectorizer (see the #ifdef ENABLE_LLVM clauses in gcc/passes.c), so you would have to

On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote: > Hi Andy, thanks for your help!! > The scheduled code by method A is same as B when using the new machine model. > it's make sense, but there is the another problem, the scheduled code is badly. > > load/store instruction always reuse the same register I filed PR17593 with this information. However, I

Hi Andy, thanks for your help!! The scheduled code by method A is same as B when using the new machine model. it's make sense, but there is the another problem, the scheduled code is badly. load/store instruction always reuse the same register Source: #define N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] =

Hi Andy, I'm working on defining new machine model for my target, But I don't understand how to define the in-order machine (reservation tables) in new model. For example, if target has IF ID EX WB stages should I do: let BufferSize=0 in { def IF: ProcResource<1>; def ID: ProcResource<1>; def EX: ProcResource<1>; def WB: ProcResource<1>; } def :

David Blaikie <dblaikie at gmail.com> 於 2020年1月6日 週一 下午2:23寫道： > If this is something that can vary per file in a compilation and resolve > correctly when one object file is built with one ABI and another object > file is built with a different ABI (that seems to be antithetical to the > concept of "ABI" Though) - then it should be a subtarget feature. > > ABI is

Hi, you need to run some optimization passes first. (like -O2) 2011/5/3 Manish Gupta <mgupta.iitr at gmail.com> > I just want to try loop-unroll and see corresponding changes in the bitcode > file. For that any loop will do. Have you been able to test llvm loop-unroll > successfully? > > > On Mon, May 2, 2011 at 10:04 PM, Yuan Pengfei <coolypf at qq.com> wrote: >

> On Jan 6, 2020, at 14:29, David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > On Mon, Jan 6, 2020 at 5:58 AM Zakk <zakk0610 at gmail.com <mailto:zakk0610 at gmail.com>> wrote: > > > David Blaikie <dblaikie at gmail.com <mailto:dblaikie at gmail.com>> 於 2020年1月6日 週一 下午2:23寫道： > If this is something that can vary per

Hi all, I meet this problem when compiling the TREAM benchmark ( http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. so I rewrite a simple code as attached link (foo.c), and compiled with two different methods: *method A:* *$clang -O3 foo.c -static -S

You mean like *llvm-gcc-4.2 -O2 -emit-llvm Hello.c -c -o Hello.bc* But still i am not able to observe any effect on bit code by running *opt-2.8 -loop-unroll Hello.bc -o Hello_unroll.bc* On Tue, May 3, 2011 at 3:58 AM, Zakk <zakk0610 at gmail.com> wrote: > Hi, you need to run some optimization passes first. (like -O2) > > 2011/5/3 Manish Gupta <mgupta.iitr at gmail.com>

On Oct 14, 2013, at 3:27 AM, Zakk <zakk0610 at gmail.com> wrote: > Hi all, > I meet this problem when compiling the TREAM benchmark (http://www.cs.virginia.edu/stream/FTP/Code/) with enable-misched > > The small function will be scheduled as good code, but if opt inline this function, the inline part will be scheduled as bad code. A bug for this is welcome. Pretty soon, I’ll

Hi, You might want to try running -loops -loop-simplify before loop unroll. >From loop simplify.cpp This pass performs several transformations to transform natural loops into a00011 // simpler form, which makes subsequent analyses and transformations simpler and00012 // more effective. Arushi On Tue, May 3, 2011 at 2:17 PM, Manish Gupta <mgupta.iitr at gmail.com> wrote: > You

David Blaikie <dblaikie at gmail.com> 於 2020年1月14日 週二 上午2:15寫道： > > > On Mon, Jan 13, 2020 at 6:12 AM Zakk <zakk0610 at gmail.com> wrote: > >> >> >> David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> 於 2020年1月11日 週六 >> 上午2:03寫道： >> >>> Ah, OK - thanks for walking me through that. >>> >>> Fair enough, I

David Blaikie via llvm-dev <llvm-dev at lists.llvm.org> 於 2020年1月11日 週六 上午2:03寫道： > Ah, OK - thanks for walking me through that. > > Fair enough, I think I understand the issue/tradeoff now - and that the > other module level metadata don't currently influence the target > configuration at this level? > > I'm not sure, I only know that the target-abi is decided

On Mon, Jan 20, 2020 at 8:05 AM Sam Elliott via llvm-dev < llvm-dev at lists.llvm.org> wrote: > To follow up on this issue: > > Our plan is still to encode `target-abi` into the module flags for RISC-V > LLVM IR modules. As was pointed out earlier in this thread, the function > lowering in Clang is slightly different for the ABIs which support hardware > floating point.

> On Jan 7, 2020, at 13:57, David Blaikie <dblaikie at gmail.com> wrote: > > > > On Mon, Jan 6, 2020 at 6:05 PM Daniel Sanders <daniel_l_sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote: > > >> On Jan 6, 2020, at 14:29, David Blaikie via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:

On Mon, Jan 27, 2020 at 3:04 PM Eric Christopher <echristo at gmail.com> wrote: > > > On Mon, Jan 27, 2020 at 2:56 PM David Blaikie via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> >> >> On Mon, Jan 20, 2020 at 8:05 AM Sam Elliott via llvm-dev < >> llvm-dev at lists.llvm.org> wrote: >> >>> To follow up on this issue:

On Tue, Jan 7, 2020 at 5:27 PM Eric Christopher <echristo at gmail.com> wrote: > > > On Tue, Jan 7, 2020 at 3:18 PM Daniel Sanders via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > >> >> >> On Jan 7, 2020, at 13:57, David Blaikie <dblaikie at gmail.com> wrote: >> >> >> >> On Mon, Jan 6, 2020 at 6:05 PM Daniel Sanders

Hi all. There are two steps in LTO codegen so the problem is how to pass ABI info into LTO code generator. The easier way is pass -target-abi via option to LTO codegen, but there is linking issue when linking two bitcodes generated by different -mabi option. (see https://reviews.llvm.org/D71387#1792169) Usually the ABI info for a file is derived from target triple, mcpu or -mabi, but in RISC-V,

Thanks a lot for your guys' help!!! I guess once I am able to get *V* (which probably is a pointer to a Value object), then, I can instrument some code at the IR level to dump V. As long as I maintain V at this pass stage, I should be able to dump the loop trip count. This is true, isn't it? Basically, what I am going to do is to add a function call before the loop body, such as:

Even after all the sequence of commands below bit-code is not showing any effect of loop-unrolling *manish at manish:~/Test2$ llvm-gcc-4.2 -O2 -emit-llvm Hello.c -c -o Hello.bc* *manish at manish:~/Test2$ opt-2.8 -loops Hello.bc -o Hello1.bc* *manish at manish:~/Test2$ opt-2.8 -loopsimplify Hello1.bc -o Hello2.bc* *manish at manish:~/Test2$ opt-2.8 -indvars Hello2.bc -o Hello3.bc* *manish at