similar to: [LLVMdev] Possibly using a broken version of GCC to build LLVM (file won't finish compiling).

Puyan, There is a doc on the document page which describe the list of broken GCCs. You'll need to check it once the docs are online. Rajika On Sun, Feb 21, 2010 at 11:33 AM, Puyan Lotfi <puyan at gatech.edu> wrote: > Hi > > Does there exist a list of relative compile times for source files in LLVM? > I am doing a build for ARM on an actual ARM device, and >

>From a cached version of the Getting Started Guide, I have found: "GCC 3.4.4 (CodeSourcery ARM 2005q3-2): this compiler miscompiles LLVM when building with optimizations enabled. It appears to work with "make ENABLE_OPTIMIZED=1 OPTIMIZE_OPTION=-O1" or build a debug build." I'm trying that now. -Puyan On Sun, Feb 21, 2010 at 1:22 AM, Rajika Kumarasiri <rajika at

Is this the configuration you would give for an iphone? -Puyan ----- Original Message ----- From: "Jim Grosbach" <grosbach at apple.com> To: "Puyan Lotfi" <puyan at gatech.edu> Cc: llvmdev at cs.uiuc.edu Sent: Wednesday, February 17, 2010 4:42:37 PM GMT -05:00 US/Canada Eastern Subject: Re: [LLVMdev] Need help getting LLVM JIT running on ARM Specifying --host,

Yes, I am not done. Please see my original message. I will send mail to the list when I am finished and then you can complain. -Tanya On Feb 20, 2010, at 10:20 PM, Rajika Kumarasiri wrote: > I just tried to access http://llvm.org/docs/ but I am getting a 404, not found error. > > Rajika > > On Fri, Feb 19, 2010 at 10:40 PM, Tanya Lattner <lattner at apple.com> wrote: >

Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? I want to use the LLVM JIT on ARM for a class project this semester. I have built and/or installed a few different gcc arm (arm-linux, and also one that is arm-elf) toolchains, and have had trouble getting LLVM 2.6 to configure and compile using the --host and --build switches of the config. If there

Hi, My name is Puyan and I've been exploring ways to improve the state of instruction level diffing using llvm and MIR. Below is a proposal for a new llvm tool meant to address issues encountered when diffing at the machine level. I'm eager to hear the community's feedback. Thanks PL mir-canon: A new tool for canonicalizing MIR for cleaner diffing. Problem Statement and

Specifying --host, --build and --target should work. For example, $ configure --host=arm-apple-darwin10 --build=i686-apple-darwin10 --target=arm-apple-darwin10 --enable-targets=arm -Jim On Feb 17, 2010, at 12:26 PM, Puyan Lotfi wrote: > Does anyone know what I should be doing if I want to cross compile LLVM for the ARM architecture? > I want to use the LLVM JIT on ARM for a class

Just a reminder that the LLVM/Clang Server will be down starting today and through most of the weekend. It will go offline sometime between 12-1pm PST. I'll send out mail when the new server is up and ready. Thanks, Tanya

I just tried to access http://llvm.org/docs/ but I am getting a 404, not found error. Rajika On Fri, Feb 19, 2010 at 10:40 PM, Tanya Lattner <lattner at apple.com> wrote: > Just a reminder that the LLVM/Clang Server will be down starting today and > through most of the weekend. It will go offline sometime between 12-1pm PST. > > I'll send out mail when the new server is up

Hi I am interested to know: are there are any LLVM targets in the works for Nvidia's PTX ISA? Also if anyone knows about Ocelot (a project done by some students at my school): it does the opposite of what I am trying to do (translates PTX to LLVM IR to run Cuda kernels on the CPU). Thanks in advance. -Puyan

Patch for review. On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> wrote: > Ping. > > Still working on preparing code for review. Will have a patch for review > ready in the coming days. > > PL > > On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com> > wrote: > >> Hi, >> >> >>

Hi I am not sure if it is possible to do something similar to what the LLVM pass framework offers (via the opt program) but in the JIT instead (when running lli). Is it possible to do any kind of online profiling (or optimization) of dynamically compiler code similar to writing an opt style code pass module? Or would I have to change a lot of stuff in the JIT? Thanks -Puyan

Hi A few of us have discussed enhancing the MIR vregs to include support for named-vregs. At the moment named regs are only supported for physical registers and number regs are reserved for vregs. We've decided that to properly implement a syntax for MIR named vregs we first need to reorganized the sigils used for physical registers and external symbols so our proposal is to swap the sigil

When we discussed this our line of thought was like this: - LLVM IR already uses %name for SSA values which is closer to what a vreg is than to what a physreg is. It would be neat to draw that parallel to llvm IR. - We wanted another sigil for physregs so they are easy to differentiate from vregs to allow people to differentiate vregs/physregs even if they don't know all the physreg names of

On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: > Hi > > I am interested to know: are there are any LLVM targets in the works > for Nvidia's PTX ISA? > > Also if anyone knows about Ocelot (a project done by some students at > my school): it does the opposite of what I am trying to do (translates > PTX to LLVM IR to run Cuda kernels on the CPU). I don't know of

Can we use %% for vregs? Seems slightly easier to remember %/%% than $/%. Also, %eax and $some_symbol are already familiar from typical assembly syntax and we probably don't want to break that association. It's all a bikeshed, but being more consistent with assembly is probably a win. -- Sean Silva On Dec 25, 2017 11:31 AM, "Puyan Lotfi via llvm-dev" < llvm-dev at

On Mon, Jan 8, 2018 at 2:27 PM, Matthias Braun <mbraun at apple.com> wrote: > When we discussed this our line of thought was like this: > > - LLVM IR already uses %name for SSA values which is closer to what a vreg > is than to what a physreg is. It would be neat to draw that parallel to > llvm IR. > - We wanted another sigil for physregs so they are easy to differentiate

The transition to the new server is complete. If you find something is broken or not working correctly, please send mail to the list (llvmdev or cfe-dev). The demo page and docs should be fully functional. Thank you for your patience during this time. Thanks, Tanya

To the list:<br /> <br /> Tons of LLVM research is being done that is damn near worthless to anyone but the person who did it because the team doesn't publish supporting code or even describe at a high level description of the algorithms they're using. And the excuse is always, ALWAYS the same: "we need to clean up the code before we release it."<br /> <br

Hi all, Many of us find ourselves spending a great chunk of time comparing LLVM IR dumps at various stages of compilation pipeline or after a given optimization pass. Said process can be extremely laborious, and this is especially true when comparing shaders or compute modules. Important semantic differences are often difficult to spot because of the irregular naming and ordering of instructions.