Displaying 20 results from an estimated 3000 matches similar to: "[LLVMdev] Master's thesis: Retargetable Compiler Backend for Transport Triggered Architectures"
2009 Mar 27
1
[LLVMdev] Announcing the Open Source Release of TTA-Based Codesign Environment (TCE) 1.0
TTA-Based Codesign Environment (TCE) is a toolset for designing
application-specific processors (ASP) based on the Transport Triggered
Architecture (TTA). TTA is a minimalistic processor architecture
template that allows high level of control for the designer to choose
the boundary between the hardware and the software.
The toolset provides a complete codesign flow from C programs down to
2010 Nov 10
0
[LLVMdev] TTA-Based Codesign Environment (TCE) v1.3 released
TTA-Based Codesign Environment (TCE) v1.3 released
--------------------------------------------------
TTA-Based Codesign Environment (TCE) is a toolset for designing
application-specific processors (ASP) based on the Transport Triggered
Architecture (TTA). The toolset provides a complete retargetable
codesign flow from C programs down to synthesizable VHDL and parallel
program binaries. Processor
2009 Mar 27
0
[LLVMdev] Announcing the Open Source Release of TTA-Based Codesign Environment (TCE) 1.0
TTA-Based Codesign Environment (TCE) is a toolset for designing
application-specific processors (ASP) based on the Transport Triggered
Architecture (TTA). TTA is a minimalistic processor architecture
template that allows high level of control for the designer to choose
the boundary between the hardware and the software.
The toolset provides a complete codesign flow from C programs down to
2012 Jun 07
0
[LLVMdev] TCE 1.6 released
TTA-based Co-design Environment (TCE) v1.6 released
---------------------------------------------------
TTA-based Co-design Environment (TCE) is a toolset for designing
application-specific processors based on the Transport Triggered
Architecture (TTA). The toolset provides a complete retargetable co-design
flow from high-level language programs down to synthesizable processor
RTL (VHDL and
2018 Mar 12
0
TTA-based Co-design Environment (TCE) v1.17 released
TTA-based Co-design Environment (TCE) is a toolset for design and
programming of low power customized processors based on the Transport
Triggered Architecture (TTA). The toolset provides a complete
retargetable co-design flow from high-level language programs down to
synthesizable processor RTL (VHDL and Verilog generation supported) and
parallel program binaries. Processor customization points
2011 Dec 13
0
[LLVMdev] TTA-based Co-design Environment (TCE) v1.5 released
TTA-based Co-design Environment (TCE) is a toolset for designing
application-specific processors based on the Transport Triggered
Architecture (TTA). The toolset provides a complete retargetable co-design
flow from high-level language programs down to synthesizable VHDL and
parallel program binaries. Processor customization points include the
register files, function units, supported operations,
2017 Sep 20
0
TTA-based Co-design Environment (TCE) v1.16 released
TTA-based Co-design Environment (TCE) is a toolset for design and
programming of low power customized processors based on the Transport
Triggered Architecture (TTA). The toolset provides a complete
retargetable co-design flow from high-level language programs down to
synthesizable processor RTL (VHDL and Verilog generation supported) and
parallel program binaries. Processor customization points
2011 Apr 11
0
[LLVMdev] TTA-Based Co-design Environment (TCE) v1.4 released
TTA-Based Co-design Environment (TCE) is a toolset for designing
application-specific processors (ASP) based on the Transport Triggered
Architecture (TTA). The toolset provides a complete retargetable co-design
flow from C programs down to synthesizable VHDL and parallel program
binaries. Processor customization points include the register files,
function units, supported operations, and the
2010 Jun 07
0
[LLVMdev] TTA-Based Codesign Environment (TCE) v1.2 released!
Announcing the Release of TTA-Based Codesign Environment (TCE) v1.2
TTA-Based Codesign Environment (TCE) is a toolset for designing
application-specific processors (ASP) based on the Transport Triggered
Architecture (TTA). The toolset provides a complete codesign flow from C
programs down to synthesizable VHDL and parallel program binaries. Processor
customization points include the register
2009 Nov 21
6
[LLVMdev] [PATCH] increase the max number of physical registers
Hello,
Attached is a trivial patch to increase the max number of physical
registers in LLVM from 1024 to 16384.
In our TCE toolset we allow the designer to choose the number of
registers in the designed TTA processors freely, and recently
while experimenting with using TTA for a GPU design we have
bumped into this limit several times.
What has made matters a bit worse for us is that we need to
2010 Jun 29
0
[LLVMdev] blog post: TCE project: Co-design of application-specific processors with LLVM-based compilation support
2010/6/29 Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi>:
> Hi,
>
> I wrote an LLVM blog post about our use of LLVM in the TCE project and a bit
> of a background for the TCE project in general. I hope some of you will find
> it interesting :)
>
> http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html
I'll ask here (rather than the TCE list)
2009 Dec 07
0
[LLVMdev] [PATCH] increase the max number of physical registers
Hello,
Can someone please commit this patch?
Thanks.
On 11/21/2009 11:15 PM, Pekka Jääskeläinen wrote:
> Hello,
>
> Attached is a trivial patch to increase the max number of physical
> registers in LLVM from 1024 to 16384.
>
> In our TCE toolset we allow the designer to choose the number of
> registers in the designed TTA processors freely, and recently
> while
2011 Jun 18
0
[LLVMdev] Custom Static Scheduling
Hi,
On 06/18/2011 06:26 AM, Benjamin Müller wrote:
> i created a Function Pass to retrieve the Control/Data Flow Graph from
> a simple program,
> now i would like to statically schedule the Instructions. Is this
> possible by starting to modify the SelectionDAG Files ?
> Or can i even build a "standalone" custom scheduler?
> Thank you very much for any tipps.
You
2009 Nov 22
0
[LLVMdev] [PATCH] increase the max number of physical registers
On Nov 21, 2009, at 1:15 PM, Pekka Jääskeläinen wrote:
> Hello,
>
> Attached is a trivial patch to increase the max number of physical
> registers in LLVM from 1024 to 16384.
>
> In our TCE toolset we allow the designer to choose the number of registers in the designed TTA processors freely, and recently
> while experimenting with using TTA for a GPU design we have
>
2007 Nov 05
6
[LLVMdev] allocating registers less "sparingly"
Hello LLVM people,
Our customizable TTA target [1] is capable of having plenty of registers
and register file ports to improve instruction level parallelism and
reduce spills. It's totally up to the designer of the particular TTA
processor how much the processor has registers and register file resources
along with other TTA components.
We have ported LLVM 2.1 to produce an intermediate TTA
2007 Nov 06
0
[LLVMdev] allocating registers less "sparingly"
On Nov 5, 2007, at 2:55 AM, Pekka Jääskeläinen wrote:
> Hello LLVM people,
>
> Our customizable TTA target [1] is capable of having plenty of
> registers
> and register file ports to improve instruction level parallelism and
> reduce spills. It's totally up to the designer of the particular TTA
> processor how much the processor has registers and register file
>
2010 Jun 29
2
[LLVMdev] blog post: TCE project: Co-design of application-specific processors with LLVM-based compilation support
Hi,
I wrote an LLVM blog post about our use of LLVM in the TCE project and a bit
of a background for the TCE project in general. I hope some of you will find
it interesting :)
http://blog.llvm.org/2010/06/tce-project-co-design-of-application.html
--
Pekka
2012 Aug 17
1
[LLVMdev] Portable OpenCL (pocl) v0.6 released
Portable OpenCL (pocl) v0.6 released
------------------------------------
Portable OpenCL aims to be an efficient open source (MIT-licensed)
implementation of the OpenCL 1.2 standard.
In addition to producing an easily portable open source OpenCL
implementation, another major goal of the project is improving
performance portability of OpenCL programs with compiler
optimizations, reducing the
2009 May 05
2
[LLVMdev] Installing tbgen with llvm by default.
Hi,
Would it be possible to set tbgen to be installed with llvm? For our
project http://llvm.org/ProjectsWithLLVM/#tta-tce it would be very
helpful, because our tools generate compiler backend plugins in the
fly for each customized processor and plugin generation needs tbgen
for handling td files.
Because of tbgen not beeing distributed, our users cannot use llvm
from their favorite
2010 Mar 17
2
[LLVMdev] vliw compatability
hi guys
I need to get llvm to support vliw architecture. Can you please point me
in the right direction. we have managed to get it to compile into simple
assemble and now need it to be able to schedule the instructions in
parrallel.
any help would be appreciated
Regards
Junior