similar to: [LLVMdev] Incorrect execution of global constructor with JIT on ARM

On 15 February 2010 14:49, Martins Mozeiko <49640f8a at gmail.com> wrote: > #include <stdio.h> > struct Global { >  typedef unsigned char ArrayType[4]; >  ArrayType value; >  Global(const ArrayType& arg) { >    for (int i = 0; i < 4; i++) this->value[i] = arg[i]; >  } > }; > static const unsigned char arr[] = { 1, 2, 3, 4 }; > static const Global

Thanks for answer, Renato. But I still thing that there is some issue with ARM codegen. When I tried running your code you modified I got exactly same LLVM IR result (verified it by comparing output from llvm-dis) - and program on runtime still produces wrong result. With some help from another developer we managed to reduce issue to following C code that is simpler: #include <stdio.h>

Hello all, I am looking at the assembly code of a loop body which is created by applying O3 optimization. Here it is: .LBB4_19: @ %for.body.91 @ =>This Inner Loop Header: Depth=1 ldr r0, [r5] mov r1, r8 add r0, r0, r7 vldr s0, [r0] mov r0, r6 vcvt.f64.f32 d0, s0 vmov

Ryan Taylor via llvm-dev <llvm-dev at lists.llvm.org> writes: > r0 gets overwritten inside the loop (assuming dst, src, src), is ldr > r0, [r5] needed to initialize r0 for the loop at each iteration? Register allocation should handle that if the load is hoisted. I'm with the others. The printf is the most likely culprit. -0David > On Thu, Mar 28, 2019

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

On Wed, 15 Apr 2020 at 03:36, John Brawn <John.Brawn at arm.com> wrote: > > > Could you please point out what am I doing wrong in the patch ? > > It's because you're getting the function name by doing > callee->getName().str().c_str() > The str() call generates a temporary copy of the name which ceases to exist outside of this expression > causing the

My home e--mail is down, which is where I get my llvm feeds, so please copy any replies to this address as well as the list. The call instruction can define implicit defs. What are the semantics when the call includes a use with a kill of some register and also an implicit def of that register? Is the register to be considered live out at that point? I've found a failing testcase where

Greetings Sandeep I have tested crosscompiling llvm2.6 svn trunk 69279 + your patch for armv7a hardware. I wanted to see if it would build and if any unexpected failing tests in the testsuite would start to work using your patch. It built fine and your attached tests in the patch runs fine for me :) Now something fun this Generic test now works that previously failed: $ llvm-as <

Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to

Hi, I have attached WIP patch for adding foldMemoryOperand to Thumb1InstrInfo. For the following case: void f(int x, int y, int z) { void bar(int, int, int); bar(x, y, z); bar(x, z, y); bar(y, x, z); bar(y, y, x); } it calls foldMemoryOperand twice, and thus converts two calls from blx to bl. callMI->dump() shows the function name "bar" correctly, however in generated

A few days ago, I tried to change the optimization flag from -O0 to -O2 to speed up the execution of the application on Ubuntu/ARM 14.04 32 bit. When I compiled the source code with -O2 flag instead of -O0 flag, I could not run the application normally by getting always the segmentation fault. Here is debugging information with GDB command in case of that. As you can see, we could not execute

Hi, I am Georg, a student for Embedded System Design at the University of Applied Sciences Upper Austria, Campus Hagenberg. (https://www.fh-ooe.at/en/hagenberg-campus/studiengaenge/master/embedded-systems-design/) In some lectures at my university, a simple 16-bit CPU with a very small instruction set of only 24 instructions called PROL16 is used to teach CPU architecture and chip design. I

Hi Tim, thanks for the swift response! @debug is defined in the same module, which makes this all the more confusing. The target information from the working example are: target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv6kz--linux-gnueabihf" from the ghc produced module: target datalayout =

When I compile the following program (for ARM): for(i=0;i<n2;i+=n3) { s+=a[i]; } , with GCC, I get the following loop body, with a post-modify load: .L4: add r1, r1, r3 ldr r4, [ip], r6 rsb r5, r3, r1 cmp r2, r5 add r0, r0, r4 bgt .L4 With LLVM, however, I get: .LBB0_3: @

Hi Bjorn, could you file a bug on llvm.org/bugs and cc me on it. Thanks, Arnold > So it appears that also the ARM backend has a big problems with sign-extending loads. > > I've compiled the following loop > > short in[]; > int out[]; > int value; > > for (i = 0; i < nr; i++) { > value = in[i]; > if (value>2047) >

Hi, Compiling attached test-case, which is reduced version of of uECC_shared_secret from tinycrypt library [1], with --target=arm-linux-gnueabi -march=armv6-m -Oz -S results in reloading of register holding function's address before every call to blx: ldr r3, .LCPI0_0 blx r3 mov r0, r6 mov r1, r5 mov r2, r4 ldr r3,

Thanks, Renato. I'm actually porting a project which is based on GAS to iOS platform. I'll report my result. Best regards! ashi On Feb 13, 2013, at 6:20 PM, Renato Golin <renato.golin at linaro.org> wrote: > I don't think there is such a document... > > There isn't a 1:1 compatibility assurance with any syntax, including the UAL and GAS, but there is good

On Fri, 7 Feb 2014, Timothy B. Terriberry wrote: > Martin Storsjo wrote: >> This is required in order to build using the built-in assembler >> in clang. > > These patches break the gcc build (with "Error: bad instruction"). Ah, right, sorry about that. > Documentation I've seen is contradictory on which order ({cond}{size} or > {size}{cond}) is correct.

Hi, I'm trying to get speex working on an ARM board (ARM926EJ-Sid(wb) core, ARM 5TE architecture) and getting segfaults if build with "--enable-fixed-point --enable-arm5e-asm" options. If I use just "--enable-fixed-point", then it runs fine, but once I add "--enable-arm5e-asm" it start crashing (I use testenc to test it). Further investigation showed, that it

On Jan 27, 2011, at 11:13 PM, Jonas Paulsson wrote: > Hi, > > I would like to transform a LLVM function containing a load and an add of the base address inside a loop to a post-incremented load. In DAGCombiner.cpp::CombineToPostIndexedLoadStore(), it says it cannot fold the add for instance if it is a predecessor/successor of the load. I find this odd, as this > is exactly what I