similar to: [LLVMdev] Illegal operations generated in ShrinkDemandedOps()

My target has only logical shifts and lacks an arithmetic right shift instruction. I have a custom LowerSRA function that rewrites SRA as SHL + SIGN_EXTEND when the shift width is either constant 16 or 24. Unfortunately, I observe that a later pass combines the SHL + SIGN_EXTEND back into SRA so we crash. The idea I had for defeating this behavior is lower to a target-specific version of SHL

Hello, I have the following loop for two data sets: diveData_2008 and diveData_2009. It uses two other data: diveCond_all and fishTable. The problem is at the point to identify the dive_id for the given index (index is timestamp). It keeps on saying for the1st loop Error in fishReport$dive_id[i] <- dive_id : replacement has length zero for the 2nd loop Error in fishReport$dive_id[i + j] <-

I'd also like to register my disappointment that the slides and videos aren't available. On Friday, October 16, 2009 4:46 PM, David Greene wrote: > When I agreed to be a speaker, I signed off on having my > talk made publicly available. There does seem to be a > double-standard here and that's concerning. There are few things about this whole situation that aren't

Hi Daniel, I want to clarify that our analysis is not based on CFL-reachability. We apply CFL-reachability to matching context information where the exist from a function to a call-site must match the entry from the corresponding call-site. The problem is a simple balanced parentheses problem in CFL-reachability, and it can be computed efficiently. The paper you mentioned is a very nice paper

Hi, One of the long-standing code clean-up bugs in Bugzilla is to extract the Machine* code from the CodeGen library into a separate one, on which CodeGen depends ( http://llvm.org/bugs/show_bug.cgi?id=1121). I'd like to start working on this. The general approach I'm planning to take is: 1. Identify which code to move. 2. Eliminate all dependencies that the Machine code has on the

Two functions in DwarfDebug, addBlockByrefAddress() and addComplexAddress(), contain this snippet of code: // Decode the original location, and use that as the start of the byref // variable's location. const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo(); unsigned Reg = RI->getDwarfRegNum(Location.getReg(), false); DIEBlock *Block = new (DIEValueAllocator) DIEBlock();

I recently subscribed to the bugs mailing list and submitted a suspected bug. The report seems to be ignored. I am guessing that it is being ignored because I am not actually an asterisk user and I am unable to supply the version or configuration of the suspect site. So then I thought I should get an account for one of the forums. I tried repeatedly to create an account but it always told me

On Tuesday, July 20, 2010 4:04 PM, Jakob Stoklund Olesen > > On Jul 20, 2010, at 10:57 AM, Ken Dyck wrote: > > > Does anybody have any tips for generating spills/reloads for large > > non-vector registers? > > [snip] > > > This is quite simple to handle. A register > MachineOperand has a subreg field for this > purpose. It is used to pick out subregisters

I'm trying to discern whether or not stack variables are all accessible through ExecutionEngine.cpp . Initially , I targeted the 'alloca' function as the source for all stack accession data , but I think that the function is too basic : ie , the type data may not be easily accessible from that function's scope . So my next idea was to use ExecutionEngine , because when data is

On Wed, Sep 11, 2013 at 12:29 AM, Andrew Trick <atrick at apple.com> wrote: > > If that is the goal, then you only want the modules for Machine IR, and maybe some core analysis passes. The “Machine” modules you listed above include machine code analysis or transform passes that you probably don’t want. Pruning the list to basic IR support: > >> - MachineBasicBlock >> -

On Tue, Mar 8, 2011 at 5:14 AM, Jacques Van Damme <Jacques.VanDamme at synopsys.com> wrote: > I am writing a backend for an architecture that has only 16-bit word > addressing (No byte addresses ever.  All data are always 16-bit). > > How can I specify this in the backend? In short, you can't. Word-addressable memory is not currently supported in LLVM (or Clang, for that

On Fri, Oct 18, 2013 at 7:27 AM, lian li <lianli at gmail.com> wrote: > Hi Daniel, > > I want to clarify that our analysis is not based on CFL-reachability. > We apply CFL-reachability to matching context information where the > exist from a function to a call-site must match > the entry from the corresponding call-site. Yes, sorry, I pulled the wrong quote, it was late.

Does anybody have any tips for generating spills/reloads for large non-vector registers? I'm working on a back end for a DSP architecture that has accumulator registers that are too large to be spilled or reloaded with a single instruction. All of their bits can be accessed in word-size chunks via three sub-registers (low, high, and ext). So loading or storing one requires three instructions:

Would there be any interest/opposition to extending the set of simple integer types in MVT to include the missing multiples of 8 (up to 64 bits)? That is: i24, i40, i48, i56? Adding the types to MVT (and ValueTypes.td) would allow LLVM to be targeted to architectures that have registers and operations of these sizes (for example, a 24-bit DSP that I'd like to develop a back end for has 24-,

Hi All, I am writing a backend for an architecture that has only 16-bit word addressing (No byte addresses ever. All data are always 16-bit). How can I specify this in the backend? As an example, consider the following instruction: %arrayidx = getelementptr [129 x i16]* @flags, i16 0, i16 %i.043 When I generate assembler code, this now results in %i.043 being multiplied by 2 in the address

What guarantees, if any, does the scheduler make when two selection nodes are linked by a Flag type? Can I expect the machine instructions that are selected from the two nodes to be scheduled consecutively? I'm trying to implement code generation for SELECT_CC nodes in a back end that I'm working on. The compare operations on the architecture communicate via bits in a global status

Just did a fresh install of CentOS 5 x86_64 on a vmware virtual box. Have done this successfully in the past but now run into problems with yum and perl CPAN. The error I get: http://centos.arcticnetwork.ca/5.0/os/x86_64/repodata/primary.xml.gz: [Errno 12] Timeout: <urlopen error timed out> Trying other mirror. continues until it runs out of mirrors. I'm able to access everything, ie:

I'm new to Centos and am in the process of building a new server. On my test box, I've installed CentOS v5 x86_64. When starting bind for the first time I found that named.conf and various zone files where missing. I installed named.conf along with localdomain.zone, localhost.zone, named.broadcast, named.ca, named.ip6.local, named.local, named.zero along with a couple test domains. The

On Dec 2, 2009, at 12:32 PM, Ken Dyck wrote: > Would there be any interest/opposition to extending the set of simple > integer types in MVT to include the missing multiples of 8 (up to 64 > bits)? That is: i24, i40, i48, i56? > > Adding the types to MVT (and ValueTypes.td) would allow LLVM to be > targeted to architectures that have registers and operations of these > sizes

On Wednesday, December 02, 2009 7:09 PM, Chris Lattner wrote: > > On Dec 2, 2009, at 12:32 PM, Ken Dyck wrote: > > > Would there be any interest/opposition to extending the set > of simple > > integer types in MVT to include the missing multiples of 8 > (up to 64 > > bits)? That is: i24, i40, i48, i56? > > > > Adding the types to MVT (and