similar to: [LLVMdev] Instruction Itineraries

Is there a way to convert between SchedMachineModel and Itineraries? I was trying to write a very simple VLIW packetizer (Hexagon was my starting point). It turns out that current DFAPacketizer is using itineraries, but my schedule is based on SchedMachineModel (I was recommended to use it since the itineraries are being phased out). I was wondering if there is an automated tool that would

Hi everyone I'm fairly new with LLVM and I've been searching around but couldn't find info on this subject. I started working on a target for a new cpu and I realizing my initial simple understanding of instruction itineraries may be completely off. I'm trying to model a CPU that has a latency of 2 cycles for multiplications fully pipelined (so it can start a new one after one

On Mon, Aug 15, 2011 at 4:03 PM, Miguel G <miguel at esenciatech.com> wrote: > Hi everyone > I'm fairly new with LLVM and I've been searching around but couldn't find > info on this subject. > I started working on a target for a new cpu and I realizing my initial > simple understanding of instruction itineraries may be completely off. > I'm trying to model a

----- Original Message ----- > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org> > To: "llvm-dev" <llvm-dev at lists.llvm.org> > Sent: Monday, November 9, 2015 10:09:07 AM > Subject: Re: [llvm-dev] Is there a way to convert between SchedMachineModel and Itineraries? > > > Anybody? Does anyone at all know how to do it? There is

It it possible to specify an instruction latency in the itinerary through a command line option? We have several options for a hardware divider which have different latencies and it would be nice if I could specify it through a compiler option rather than changing the value in the code and recompiling llvm every time? Any help is appreciated. -- Rail Shafigulin Software Engineer Esencia

All, I'm working on a new scheduler. I have a basic block for which my scheduler generates bad code. The C code looks like int j, *p; if ((j = *p++) != 0) {...} My scheduler emits (x86, AT&T) mov p, %rax mov (%rax), %rax mov %rax, j addq $0x04, p je ... Notice there is no test instruction. The default list scheduler generates mov p, %rax mov (%rax), %rax mov %rax, j addq $0x04,

We improved our instruction itineraries and now we're seeing our testcases for fence instructions break. For example, we have this testcase: @write_me = external global i32 @read_me = external global i32 ; Function Attrs: nounwind define i32 @xstg_intrinsic(i32 %foo) #0 { entry: ; CHECK: store r0, r1, 0, 32 ; CHECK-NEXT: fence 2 %foo.addr = alloca i32, align 4 store i32 %foo,

On Mon, Aug 22, 2016 at 11:40 AM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > > On Aug 22, 2016, at 11:20, Phil Tomson via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > > > We improved our instruction itineraries and now we're seeing our > testcases for fence instructions break. > > > > For example, we have this testcase: > >

> On Nov 9, 2015, at 10:49 AM, Rail Shafigulin <rail at esenciatech.com> wrote: > > On Mon, Nov 9, 2015 at 10:31 AM, Hal Finkel <hfinkel at anl.gov <mailto:hfinkel at anl.gov>> wrote: > ----- Original Message ----- > > From: "Rail Shafigulin via llvm-dev" <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> > > To:

All, Where are the SSE instructions defined? Specifically, I cannot find the def for ADDSDrr. Aran -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 194 bytes Desc: This is a digitally signed message part. URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100326/130b2e02/attachment.sig>

We have a two different dimensions for each instruction: slot assignments, and operand timings. These two are unrelated to each other, and also each (or both) can change for any given instruction from one architecture version to the next. The main concern for us was which of these mechanisms contains all the information that we need. We cannot express all the scheduling details by hand, and

Hi Krzysztof, 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org>: > > > On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using

On Apr 26, 2013, at 3:53 AM, Martin J. O'Riordan <Martin.ORiordan at movidius.com> wrote: > I am migrating the llvm/clang derived compiler for our processor from the > v3.1 to v3.2 codebase. This has mostly gone well except that instruction > latency scheduling is no longer happening. > > The people who implemented this previously sub-classed 'ScheduleDAGInstrs'

All, I'm trying to build llvm-gcc 4.2 from svn (as of about a week ago). I'm getting: ../../llvm-gcc-4.2/libcpp/expr.c: In function 'num_negate': ../../llvm-gcc-4.2/libcpp/expr.c:1114: internal compiler error: Segmentation fault Please submit a full bug report, with preprocessed source if appropriate. I would like to do some debugging, but I don't see where

All, I've been working on a new scheduler and have somehow affected register selection. My problem is that an xmm register is being used as an index expression. Specifically, addss (%xmm1,%rax,4), %xmm0 I like the idea of a floating-point index, but, like the assembler, I don't know what that means. Any suggestions on where I should look for a solution to my problem?

I'm unclear how does DFAPacketizer and the scheduler know a given instruction is a load. Here is what I'm talking about Let's assume my VLIW target is described as follows: def MyTargetItineraries : ProcessorItineraries<[Slot0, Slot1], [], [ .............................. InstrItinData<RI, [InstrStage<1, [Slot0, Slot1]>]>,

Thanks Eli. Somehow I was assuming the scheduler would insert NOPs to enforce latencies The CPU I'm dealing with doesn't automatically stall, i.e. latency must be ensured by the program. As an alternative to a pass, is it feasible to modify the scheduler to do so (optionally) or it would be too complicated. If possible, what would be the right place to look ? Thanks so much Miguel On

> On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using itineraries. I wanted to understand the benefit in using itineraries over the per operand scheduling. > > I

Hello Hal. > Is there a way to express a multiple pipeline itinerary using the > current scheme Yes, surely > (maybe some trick with setting NextCycles = 0)? Yep! > Specifically, consider a case where a floating-point load simultaneously > uses units from a floating-point pipeline and a load/store pipeline. Look into ARM itineraries, they contain a decent amount of such examples.

On Sep 23, 2011, at 6:16 AM, Ghassan Shobaki wrote: > Hi Andrew, > > What we have is not a patch to any of LLVM's schedulers. We have implemented our own scheduler and integrated it into LLVM 2.9 as yet-another scheduler. Our scheduler uses a combinatorial optimization approach to balance ILP and register pressure. In one experiment, we added more precise latency information for