similar to: [LLVMdev] Adding instruction to mips backend

What sorts of errors are you seeing? My first guess would be that you need to add support for the new instruction to the SelectionDAG machinery (see lib/CodeGen/SelectionDAG/*). What instruction are you looking to add? On Feb 1, 2010, at 3:11 AM, Daniel Hallmannseder wrote: > Hi, > > I've extended the LLVM IR with a new Instruction. This part works well. > But I also want to

Hello all, I would like to restrain the compiler that I build on my local box from picking all but a particular set of opcodes. Is there a way to accomplish this in a straightforward way? I'm pretty sure that there is a list of opcodes to semantics mappings. In addition, is there a way to look at an associative mapping of LLVM IR to opcode, and/or vice versa? -------------- next part

Hi, if I want to know how switch instructions are handled in the backend, where do I have to look first? I'm not familiar with the backend framework and I couldn't figure out the interface between the LLVM instruction 'SwitchInst' and whatever there is in the backend. I would be very happy about every hint where I have to look to find the entry point of switch instructions in the

On Fri, Jun 3, 2016 at 11:53 AM, Ahmed Bougacha <ahmed.bougacha at gmail.com> wrote: > -llvmdev at cs.uiuc.edu, that list isn't in use anymore. > > On Wed, Jun 1, 2016 at 4:48 PM, Kenneth Adam Miller via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > Hello all, > > > > I would like to restrain the compiler that I build on my local box from >

> On Nov 19, 2015, at 4:58 PM, Eric Christopher <echristo at gmail.com> wrote: > > > > On Thu, Nov 19, 2015 at 2:26 PM Quentin Colombet <qcolombet at apple.com <mailto:qcolombet at apple.com>> wrote: > Hi Eric, > > >> On Nov 19, 2015, at 12:46 PM, Eric Christopher <echristo at gmail.com <mailto:echristo at gmail.com>> wrote: >>

Hello, I'm working on the text of my Master's Thesis and I have some doubts: 1. What algorithm is used in Selection Instruction ? What is the input ? 2. Where is described how the variations of List Scheduling work, in -pre-RA-sched phase ? -pre-RA-sched - Instruction schedulers available (before register allocation): =source -

> > The other thing that might work, is having TargetMachine remember how > > the fast-isel option got set, and make OptLevelChanger do the right > > thing. But that seems like a hack to work around Mips not obeying the > > specified optimization level, honestly. > > I think we should do that as well. I don't think it's right that optnone > enables Fast

Hi, I'm looking at writing a custom backend targetting a proprietary virtual machine. I'm basing it on the existing C and MSIL backends. My VM only has 32- and 64-bit integer operations (like the JVM) but C code compiled with llvmgcc typically has lots of 1-, 8- and 16-bit instructions. I was thinking of writing a custom pass to promote small integer types and instructions to 32-bits,

Andrew Lenharth wrote: > On Fri, 2005-03-18 at 05:04 +0900, Duraid Madina wrote: >> - No varargs > > What are your issues here? Or are they simply at the "not implemented > so I don't know" stage? The two bugs I mentioned (no varargs, no alloca) are pretty much two sides of the same coin: I'm ignoring the IA64 stack frame layout (for no good reason), so

On Dec 11, 2017 6:54 PM, "Sean Silva" <chisophugis at gmail.com> wrote: It looks like in various places in SelectionDAG and related machinery we appear to implicitly or explicitly assume that TypeExpandInteger only applies to scalars. Does anybody know why that is? For our target (Pixel Visual Core: https://www.blog.google/ products/pixel/pixel-visual-core-image-processing-and-

The driving goal of 'optnone' is to have an easy way for programmers to get an "-O0 like" debugging experience for selected functions, without making them build everything with –O0. To that end, we turn off as much optimization as we reasonably can, but in the context of a pipeline that is generally expecting optimizations to be enabled, in practice we can't exactly match –O0

Well, 'optnone' is already not identical to -O0, and given the nature of things, probably can't be; but I am persuaded that it's reasonable for it to honor the -fast-isel option as a debugging tactic. I'll take an AI to make this happen. Thanks, --paulr P.S. One nit, the "O0 + optnone" case should not have an asterisk, the FastISel flag is not manipulated if the opt

Hey Tom, Really it was at the behest of the replies - we got a lot of feedback from the mailing list that indicated we'd be putting extra workload of people changing features of the IR if we didn't follow the same mechanisms of the other backends (mostly led by Chandler's very astute comments on the subject). Cheers, -Neil. On 07/07/15 14:43, Tom Stellard wrote: > On Tue, Jul

On Fri, 18 Mar 2005, Duraid Madina wrote: >>> - No instruction scheduling/bundling of any sort >> >> So this one needs to be coordinated. Next week, I might see about >> adding MachineInstruction support to the SelectionDAG so you can load up >> a DAG post-ISel and then spit it back out scheduled. > > That would be much appreciated, particularly if it

I was mucking around in FastISel, and was surprised to see the test llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll failed. This was surprising because it specifies -fast-isel=false. Does the Mips code generator use fast-isel even when you ask it not to? Thanks, --paulr

On Fri, 11 Mar 2005, Morten Ofstad wrote: > Hello, > > I am trying to make the FP intrinsics (abs, sin, cos, sqrt) I've added work > with the X86ISelPattern, but I'm having some difficulties understanding what > needs to be done. Cool. Here are a couple of requests: 1. I don't think we need an "llvm.abs" intrinsic at the llvm level. This can be

> > I was mucking around in FastISel, and was surprised to see the test > > llvm/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll > > failed. This was surprising because it specifies -fast-isel=false. > > > > Does the Mips code generator use fast-isel even when you ask it not to? > > Thanks, > > --paulr > > This seems to be an all-targets bug.

Hi, Dan Someone on the irc suggest me using custom lowering to do the mapping correctly. But I am still trying to figure out how to do that. Regards, chenwj -- Wei-Ren Chen (陳韋任) Computer Systems Lab, Institute of Information Science, Academia Sinica, Taiwan (R.O.C.) Tel:886-2-2788-3799 #1667

Hi llvm-dev, In the review of the LLVM-side changes to support XRay (which is now upstream as http://reviews.llvm.org/rL275367) we hit one particular case where we had to hack around the fact that we have no way to force the emission of a short relative jump. It's even come up that jump relaxation can come in and (at least with clang -O0) relax jumps to use the longer version of the jump

Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile -