Displaying 20 results from an estimated 500 matches similar to: "[LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg."
2010 Jan 25
0
[LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg.
2010/1/25 任坤 <hbrenkun at yahoo.cn>:
> Hi:
>
> I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks.
>
> 1. MachineDominatorTree *domintree = new MachineDominatorTree();
> domintree->runOnMachineFunction(mf);
>
> 2. Then travel mf one by one.
> When domintree->dominates(next,current) is true, there is a backedge
2010 Mar 09
1
[LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg.
Hi:
I want to do some optimization on MachineLoop.
So I want to get MachineLoopInfo from MachineFunction.
I reference MachineLICM.cpp.
So I try to write a pass in Target/mytarget directory.
I find there is Error.
llvm/include/llvm/PassAnalysisSupport.h:198: AnalysisType& llvm::Pass::getAnalysisID(const llvm::PassInfo*) const [with AnalysisType = llvm::MachineLoopInfo]: Assertion
2010 Jan 26
1
[LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg.
Hi, Dear Boissinot:
1. When I have irreducible CFG, I travel its nodes by DFS.
search backedge for every node. After I finish one node,
push it into a stack.
[0, 1, 2, M] <---push.
[0, 1, 2, M,...N] <---push.
When resolving node M, find a edge from node N to node M,
N is not in stack(M < N), It is a backedge.
N is in stack(M > N), It is NOT a backedge.
2010 Mar 09
1
[LLVMdev] Find all backedges of CFG by MachineDominatorTree. please look at my jpg.
Thank you, Nick.
Yes, I have add getAnalysisUsage.
As I know, some CFG is irreducible.
At this time, Dominator Tree can not find
some backedge. Is it means some MachineLoop is
not be found?
dominatorTree.jpg is a previous exmaple.
best regards!
renkun
--- 10年3月9日,周二, Nick Lewycky <nicholas at mxc.ca> 写道:
> 发件人: Nick Lewycky <nicholas at mxc.ca>
> 主题: Re: [LLVMdev] Find
2010 Jan 25
0
[LLVMdev] About MachineDominatorTree Pass.
Hi:
I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks.
1. MachineDominatorTree *domintree = new MachineDominatorTree();
domintree->runOnMachineFunction(mf);
2. Then travel mf one by one.
When domintree->dominates(next,current) is true, there is a backedge from current node to next node. move this backedge form CFG.
But I find A LOOP in
2009 Dec 04
4
[LLVMdev] hi, Hi, (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really?
Hi, EveryOne:
I am travelling CFG with MachineFunction. So I want to sure it.
(Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really?
best regards.
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2009 Dec 04
0
[LLVMdev] hi, Hi, (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really?
On Dec 3, 2009, at 9:52 PM, 任坤 wrote:
> I am travelling CFG with MachineFunction. So I want to sure it.
> (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really?
If the CFG contains loops, how could this be possible?
Anyway, no you can't use MBB numbers for that. Perhaps you need the MachineDominatorTree analysis?
Regards,
/jakob
2009 Mar 31
1
[LLVMdev] 转发: Re: Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
Dear Evan Chang:
I register incorrect Register class for MVT::f64. I have fixed it. Thanks your advice.
"-view-legalize-dags" is very good option.
But I don't know why my LLC do not know " -view-legalize-type-dags" option.
By the way, I use llvm 2.5 merged from llvm2.4.
Best Regards,
Ren Kun
--- 09年3月31日,周二, Evan Cheng <echeng at apple.com> 写道:
发件人: Evan Cheng
2009 Dec 04
0
[LLVMdev] hi, Hi, (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really?
On Dec 3, 2009, at 9:52 PM, 任坤 wrote:
> Hi, EveryOne:
>
> I am travelling CFG with MachineFunction. So I want to sure it.
> (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really?
>
Hi 任坤,
I can't say for sure, though I don't think we make assurances that this is the case. If you want to traverse the CFG, there should
2009 Feb 20
2
[LLVMdev] help: about how to use tblgen to constraint operand.
hi, Dear Evan Cheng:
My cpu is i32 embeded CPU. I define pseudo register pair registers.
In mytargetRegisterInfo.td:
def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
...
def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
In mytargetISelLowering.cpp:
I define i1, i8 , i16 and i32 are legal.
1. I still have problem. I save my function return double value in
2009 Mar 30
1
[LLVMdev] Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
I try to define a register class
def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
to simulate even/odd pair of GPR32 register.
Actually, I just use GPR64 as a temporary register.
My CPU just support i32 Integer type directly.
I use FDR to save f64.
def FDR : RegisterClass<"mytarget", [f64], 64,[FD0, FD1, ....]
When I move f64 to even/odd pair register, I
2009 Feb 20
0
[LLVMdev] help: about how to use tblgen to constraint operand.
On Feb 19, 2009, at 8:26 PM, 任坤 wrote:
> hi, Dear Evan Cheng:
>
> My cpu is i32 embeded CPU. I define pseudo register pair registers.
>
> In mytargetRegisterInfo.td:
> def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
> ...
> def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
>
> In mytargetISelLowering.cpp:
> I define i1, i8 ,
2010 Jan 15
0
[LLVMdev] <IsKill> getting from MachineOperand is just <Used> attribute from logic.
On Jan 14, 2010, at 6:39 PM, 任坤 wrote:
> But I want do some optimization after register alloction by adjusting
> register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg.
You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same
2010 Jan 15
2
[LLVMdev] <IsKill> getting from MachineOperand is just <Used> attribute from logic.
Hi,
I have ported LLC to a risc cpu. It can pass benchmark that I have at current.
But I want do some optimization after register alloction by adjusting
register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg.
R4 is marked <kill> at MBB0. If I scan R4's
2009 Sep 24
0
[LLVMdev] About porting llvm-gcc frontend.
Hi 任坤,
> void vfu1(union MYunion u) {
> u.ui = 99;
> }
here u is passed by copy, so vfu1 has no externally
visible effect. I think you meant: union MYunion *u
> define void @vfu1(%struct.MYunion* byval align 4 %u) nounwind {
Here "byval" means that a pointer to a temporary copy of u is being
passed, not u itself. Thus any writes to the %u parameter have no
effect
2007 Dec 10
1
[LLVMdev] MachineDominatorTree
Hi, guys,
what is the interface for finding the immediate dominator of a machine
basic block in LLVM 2.1? I found some methods to check if a node dominates
other in llvm::MachineDominatorTree, but I was looking for something like:
MachineBasicBlock * mbb = ...
MachineBasicBlock * iDom = XXX->getImmediateDominator(mbb);
is there something similar?
best,
Fernando
2009 Sep 23
2
[LLVMdev] About porting llvm-gcc frontend.
I am porting llvm-gcc frontend. We have ported GCC4.2 for our target. So I move *.h *.md and *.c to llvm-gcc. I do not implement any LLVM MACRO, and use default action of llvm-gcc. I get a new llvm-gcc for our target. But I get a bug.
/******************************/
//#include <stdio.h>
union MYunion {
unsigned char uc ;
int ui;
} myunion;
void vfu1(union MYunion u) {
u.ui =
2008 Dec 03
4
[LLVMdev] Identifying backedges
Hi,
How do I find out if a branch instruction belongs to an if-else or a loop i.e it is a backedge.
Thanks,
Bhavani
2008 Dec 03
0
[LLVMdev] Identifying backedges
Bhavani,
A simple way that I'm not sure is 100% guaranteed to work is if the
branch is to an earlier or later basic block.
Micah
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of bhavani krishnan
Sent: Wednesday, December 03, 2008 3:20 PM
To: Nick Lewycky; LLVM Developers Mailing List
Subject: [LLVMdev] Identifying
2010 Mar 16
1
[LLVMdev] LoopSimplify : why to separate a loop with multiple backedges into a nested loop ?
Hello,
LoopSimplify try to separate a loop with multiple backedges into a
nested loop (an outer loop and an inner loop).
Naturally, this kind of a loop corresponds to a single loop in source
code. I can see this could be useful for cases described in the
comments in lib/Transforms/Utils/LoopSimplify.cpp, which looks like a
corner case. For most cases,
how does this help ?
Junjie