similar to: [LLVMdev] llvm opt phase ordering

Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] llvm opt phase ordering"

2011 Nov 15
1
[LLVMdev] opt -O2 optimization passes
Hi all, I would like to know which optimization passes are performed at -O2 by opt. So I used following command: llvm-as < /dev/null | opt -O2 -std-compile-opts -disable-output -debug-pass=Arguments I've got following output for LLVM opt 2.9: Pass Arguments: -no-aa -tbaa -basicaa -simplifycfg -domtree -scalarrepl -early-cse Pass Arguments: -targetlibinfo -no-aa -tbaa -basicaa
2009 Feb 02
1
[LLVMdev] Proposal: Debug information improvement - keep the line number with optimizations
Hi, I've been thinking about how to keep the line number with the llvm transform/Analysis passes. Basically, I agree with Chris's notes ( http://www.nondot.org/sabre/LLVMNotes/DebugInfoImprovements.txt), and I will follow his way to turn on the line number information when optimization enabled. Here is a detailed proposal: 1. Introduction At the time of this writing, LLVM's
2005 Apr 22
0
[LLVMdev] Need help with bugpoint for codegen problem
On Fri, Apr 22, 2005 at 02:32:25AM +0200, Markus F.X.J. Oberhumer wrote: > Ok, after pasting the output from "gccas -debug-pass=Arguments > </dev/null -o - >/dev/null" I get the following: > > bugpoint -verify -lowersetjmp -funcresolve -raiseallocs -simplifycfg > -mem2reg -globalopt -globaldce -ipconstprop -deadargelim -instcombine > -simplifycfg -prune-eh
2011 Oct 07
2
[LLVMdev] MIPS 32bit code generation
Hi, I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks, On Thu, Oct 6, 2011 at 11:29 AM, Akira Hatanaka <ahatanak at gmail.com> wrote: > Do you want to replace > > lui $2, %hi(g1) > addiu $2, $2, %lo(g1) > > with this? > la $2, g1 > > If that
2006 Mar 21
0
[LLVMdev] problem loading analysis results from Inliner pass
A On 3/21/06, Michael McCracken <michael.mccracken at gmail.com> wrote: > On 3/21/06, Chris Lattner <sabre at nondot.org> wrote: > > On Mon, 20 Mar 2006, Michael McCracken wrote: > > > > > Hi, I'm trying to access an analysis pass from the Inliner pass, and > > > I'm having a lot of trouble getting that to work - I can verify that > >
2010 Jan 13
2
[LLVMdev] Cross-module function inlining
I've developed a working LLVM back-end (based on LLVM 2.6) for a custom architecture with its own tool chain. This tool chain creates stand-alone programs from a single assembly. We used to use GCC, which supported producing a single machine assembly from multiple source files. I modified Clang to accept the architecture, but discovered that clang-cc (or the Clang Tool subclass inside Clang)
2011 Oct 07
1
[LLVMdev] MIPS 32bit code generation
I don't think I ever said that the MIPS target is broken. I am simply trying to branch out one additional llc target for SimpleScalar PISA architecture. On Fri, Oct 7, 2011 at 2:41 PM, Jim Grosbach <grosbach at apple.com> wrote: > I reiterate. You should fix the simulator. It is broken. The compiler is > not. Fix what's broken. > > -Jim > > On Oct 7, 2011, at 1:11
2010 Jan 13
0
[LLVMdev] Cross-module function inlining
Mark Muir wrote: > I've developed a working LLVM back-end (based on LLVM 2.6) for a custom architecture with its own tool chain. This tool chain creates stand-alone programs from a single assembly. We used to use GCC, which supported producing a single machine assembly from multiple source files. > > I modified Clang to accept the architecture, but discovered that clang-cc (or the
2011 Oct 07
0
[LLVMdev] MIPS 32bit code generation
I reiterate. You should fix the simulator. It is broken. The compiler is not. Fix what's broken. -Jim On Oct 7, 2011, at 1:11 PM, Gang-Ryung Uh wrote: > Hi, > > I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks, > > > > On Thu, Oct 6, 2011 at
2011 Oct 05
4
[LLVMdev] MIPS 32bit code generation
Hi, In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Thanks, -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
Do you want to replace lui $2, %hi(g1) addiu $2, $2, %lo(g1) with this? la $2, g1 If that is the case, you can add this pattern. def op_la : Operand<i32>; def LA : FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), "la $dst, $addr0", [(set CPURegs:$dst, (add (MipsHi tglobaladdr:$addr0), (MipsLo tglobaladdr:$addr1)))], IIAlu>;
2009 Jan 25
0
[LLVMdev] -O4 limitations in llvm/llvm-gcc-4.2 2.5?
Jack Howarth wrote: > I've had better luck compiling all of pymol 1.1r2 with > -O4 on darwin9. Everythink links and there appears to be > no regressions in the resulting code. I take it that LTO > in llvm 2.5 is still limited to dead code elimination, > correct? No. libLTO does the equivalent to opt -internalize -ipsccp -globalopt -constmerge -deadargelim -instcombine
2006 Mar 21
3
[LLVMdev] problem loading analysis results from Inliner pass
On 3/21/06, Chris Lattner <sabre at nondot.org> wrote: > On Mon, 20 Mar 2006, Michael McCracken wrote: > > > Hi, I'm trying to access an analysis pass from the Inliner pass, and > > I'm having a lot of trouble getting that to work - I can verify that > > my pass is loaded and run (it is a dynamically loaded pass that is > > part of an analysisgroup),
2008 Dec 04
0
[LLVMdev] 32bit math being promoted to 64 bit
instcombine doesn't seem to be doing it. From my testing it seems to only occur when I use -indvars after a long string of commands. For example: llvm-as < test_fc_27.ll | opt -preverify -domtree -verify -lowersetjmp -raiseallocs -simplifycfg -domtree -domfrontier -mem2reg -globalopt -globaldce -ipconstprop -deadargelim -instcombine -simplifycfg -ba siccg -prune-eh -inline
2007 Jul 18
1
[LLVMdev] llvm-ld doesn't honor -Ox
The project that I use to test LLVM against showed that currently llvm-ld doesn't honor the -Ox switch. $ /usr/src/llvm/dist/bin/llvm-ld \ -v -stats -native -O1 -strip-all \ -o main \ -L/usr/share/qt3/lib -L/usr/X11R6/lib \ -lcrypto -lusb -lutil -lqt-mt -lXext -lX11 -lm -lpthread ... $ size main text data bss dec hex filename 1128271 71980 8392 1208643 127143
2011 Oct 06
1
[LLVMdev] MIPS 32bit code generation
Hi, for our micro-architecture research, we are using simplescalar 3.0 32bit mips simulator, which comes with binutils 1.5.2, and the ld fails at "lui" (bfd error). However, the ld is happy with "la" (assembler macro) and simulator correctly simulates. On Wed, Oct 5, 2011 at 5:04 PM, Eric Christopher <echristo at apple.com> wrote: > > On Oct 5, 2011, at 4:01 PM,
2011 Jul 15
2
[LLVMdev] LLVM and little-endian 32-bit MIPS code generation
Hi, We have tried and generate assembly code for very simple test C code. But, binutils-2.5.2 (simplesim-3.0) cannot handle the produced assembly code with the following complaints. Could you advise which version of bitutils that we need to use for mips code with LLVM with Clang? Thanks, $ GCC addr01.s addr01.s: Assembler messages: addr01.s:1: Error: Unknown pseudo-op: `.section'
2016 May 09
2
Some questions about phase ordering in OPT and LLC
On Mon, May 09, 2016 at 01:07:07PM -0700, Mehdi Amini via llvm-dev wrote: > > > On May 9, 2016, at 10:43 AM, Ricardo Nobre via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > > Hi, > > > > I'm a PhD student doing phase ordering as part of my PhD topic and I would like to ask some questions about LLVM. > > > > Executing the following
2011 Jul 11
0
[LLVMdev] LLVM and little-endian 32-bit MIPS code generation
It will produce little-endian code if you replace "mips" with "mipsel". 1. clang -ccc-host-triple mipsel-unknown-linux -ccc-clang-archs mipsel -O3 -S -emit-llvm foo.c -o foo.ll 2. llc -march=mipsel -mcpu=4ke foo.ll -o foo.s (the -march option is redundant) If you do not specify the target cpu with -mcpu, by default it will generate code for Mips1, which has not been tested as
2011 Jul 09
2
[LLVMdev] LLVM and little-endian 32-bit MIPS code generation
We are trying to use LLVM (Clang as the C frontend) to generate code for 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 sslittle-na-sstrix platform. Can you advise what would be the right way to use the LLVM compiler infrastructure? The following is the one I used, but it appears that it produce the code in big-endian (and I wonder whether the calling convention is right.) To