similar to: [LLVMdev] Setting TARGET_LLCFLAGS in the environment

On Jan 11, 2010, at 3:50 PM, Jakob Stoklund Olesen wrote: > Weird issue beyond my make-fu: > > When running the test-suite, this works fine: > > make TARGET_LLCFLAGS='-mcpu=cortex-a8 -mattr=+thumb2' TEST=nightly report > > But this fails: > > export TARGET_LLCFLAGS='-mcpu=cortex-a8 -mattr=+thumb2' > make TEST=nightly report > > It looks

Hi all, Does llc -march=thumb -mcpu=cortex-a9 enable generation of thumb2 code for armv7 ? Best Regards Seb -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120727/da758ea0/attachment.html>

Here is a one-line patch to support the cortex-m3. For those who plan the features for ARM, the new cortex-m0 implements only a subset of the Thumb2 instructions. I still have yet to see a document that details what's in the subset. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: arm.diff URL:

On Jul 27, 2012, at 9:04 AM, Sebastien DELDON-GNB <sebastien.deldon at st.com> wrote: > Hi all, > > Does llc –march=thumb –mcpu=cortex-a9 enable generation of thumb2 code for armv7 ? That's how I usually do it. Somewhere in the target description we associate a9 with -mattr=+thumb2. There are plenty of other ways to get the same result, and it's all very confusing and

On 8 December 2016 at 02:34, Jojo Ma <jojo.ma at linaro.org> wrote: > It would be profitable as well if we could enable the canonicalisation on > it. > sequence before this canonicalisation (ARM): > test: > .fnstart > @ BB#0: @ %entry > movw r1, #65534 > and r1, r0, r1 > ubfx r0, r0, #1, #15 > add r0, r0, r1, lsr #1 > bx lr

This is with Linux on BeagleBone Black (Cortex-A8), regressed recently: FAIL: LLVM :: MC/ARM/basic-arm-instructions.s (5404 of 8944) ******************** TEST 'LLVM :: MC/ARM/basic-arm-instructions.s' FAILED ******************** Script: -- /havana/work/llvm/build/Release+Asserts/bin/llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding <

Hi James, Thanks for the answer, can you elaborate on difference between thumb, thumb2, ARM, thumbv7. I'm a bit lost right now. When specifying thumbv7 llc will generate thumb only code, not thumb2 ? Best Regards Seb > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of James Molloy > Sent: Tuesday, May 29,

Tim Northover <t.p.northover at gmail.com> writes: >> /tmp/foo.s:1:2: error: instruction requires: distinct-ops >> sllk %r2,%r3,1 >> ^ > > That seems like it would be a good improvement for all targets. Thanks, sounds like it might be more acceptable than I thought :-) >> ARM seems to rely on the current MatchOperandParserImpl() behaviour,

Thanks andrew for the answer. I would like to generate code for Cortex-A9 that don't use neon for fp computation but vfpv3 -d16. I've tried some combination of -mattr=+neon,-neonfp,+vfp3,+d16 but couldn't get ".fpu vfpv3-d16" directive generated in assembly file. Do you know how to make it happen ? Best Regards Seb From: Andrew Trick [mailto:atrick at apple.com] Sent:

Hi! The rewrite of the attributes class is well underway. The next step is to add support for the expanded rôle of attributes in the language and IR. This is the final proposal for the language changes. There isn't a lot of new information except for the syntax changes for the new feature. Executive Summary: The new syntax is: #0 = attributes { noinline align=4

Hi Seb, The ARM instruction set is a fixed-width 32-bit instruction set that has been around since the early days of ARM. Modern (armv4t onwards) cores mostly have another instruction set that can be used in tandem, the "thumb" instruction set. This is a variable width (16 or 32 bit) instruction set that provides a subset of the ARM instruction set and was intended to provide the

Hi James, Thanks for the answer, for Cortex-A9 would you recommend to generate thumb2 code or ARM code ? What would be the best performance wise ? Best Regards Seb > -----Original Message----- > From: James Molloy [mailto:james.molloy at arm.com] > Sent: Thursday, May 31, 2012 9:57 AM > To: Sebastien DELDON-GNB > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] llc support

The thumb2 instructions include unsigned and signed divide. Attached are a patch and test routine. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: div.diff URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091201/675cf4c5/attachment.ksh> -------------- next part -------------- An embedded and charset-unspecified text was

On 12/16/14 3:53 AM, Kristof Beyls wrote: > I've been wondering too about how to get better ARM v6m compile-and-execute > testing going. > > As you say Jon, the non-execution-based regression tests are surprisingly > good at catching issues; but they're no full substitute for executing the > code produced by the backend for a reasonably-sized test suite. > > If

Both Clang/LLVM 3.4 -> Clang/LLVM 3.5 And i will also try using MCJIT. 2014-09-17 18:56 GMT+06:00 Anton Smirnov <dev at antonsmirnov.name>: > Hi, Tim. > > I've used Clang 3.4 final release and now i'm going to test it with 3.5 > release (since i've read about arm64 improvements). > I will report my results. > > BTW, is it possible to get smth like

Looks OK to me, but I don't have any Cortex-M3 docs to confirm the choice of v7-A without NEON. deep On Sun, Nov 22, 2009 at 9:47 PM, Bagel <bagel99 at gmail.com> wrote: > Here is a one-line patch to support the cortex-m3. > For those who plan the features for ARM, the new cortex-m0 implements only a > subset of the Thumb2 instructions.  I still have yet to see a document that

On 23 July 2012 17:03, Chris Cadwallader <ccadwallader at arxan.com> wrote: > On Darwin, if -march is armv7 clang's driver will assume you want thumb2 unless you also give it -mno-thumb but that is irrelevant with mcpu=cortex-m3. I think that Thumb2 should be the default for v7 on any system, not just Darwin. Maybe some ARM folk can comment on this... -- cheers, --renato

On 08/02/13 14:42, Renato Golin wrote: [...] > Can you paste the result of a "clang -v -mcpu=CPU file.c" on your box? I > want to see what are the arguments and the assembler/linker it's > choosing to use. What CPU are we talking about? The box itself is an Allwinner A10; armv7l. /proc/cpuinfo says it's got swp half thumb fastmult vfp edsp neon vfpv3. I've been

Motivation At the moment, when targeting armv7a, clang defaults to generate code as if -mcpu=cortex-a8 was specified. When targeting armv8a, it defaults to generate code as if -mcpu=cortex-a53 was specified. This leads to surprising code generation, by the compiler optimizing for a specific micro-architecture, whereas the intent from the user was probably to generate code that is

On Jan 29, 2013, at 2:42 PM, Bill Wendling <isanbard at gmail.com> wrote: > Executive Summary: > > The new syntax is: > > #0 = attributes { noinline align=4 "cpu"="cortex-a8" } > #1 = attributes { attr = (val1 val2 val3) } > #bork = attributes { sspreq noredzone } > > define void @foo() #0 #bork { ret void } The general syntax LGTM. It