similar to: [LLVMdev] Debugging LLVM opt pass

Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] Debugging LLVM opt pass"

2011 Oct 07
2
[LLVMdev] MIPS 32bit code generation
Hi, I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks, On Thu, Oct 6, 2011 at 11:29 AM, Akira Hatanaka <ahatanak at gmail.com> wrote: > Do you want to replace > > lui $2, %hi(g1) > addiu $2, $2, %lo(g1) > > with this? > la $2, g1 > > If that
2011 Oct 05
4
[LLVMdev] MIPS 32bit code generation
Hi, In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Thanks, -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh
2011 Oct 07
1
[LLVMdev] MIPS 32bit code generation
I don't think I ever said that the MIPS target is broken. I am simply trying to branch out one additional llc target for SimpleScalar PISA architecture. On Fri, Oct 7, 2011 at 2:41 PM, Jim Grosbach <grosbach at apple.com> wrote: > I reiterate. You should fix the simulator. It is broken. The compiler is > not. Fix what's broken. > > -Jim > > On Oct 7, 2011, at 1:11
2011 Oct 07
0
[LLVMdev] MIPS 32bit code generation
I reiterate. You should fix the simulator. It is broken. The compiler is not. Fix what's broken. -Jim On Oct 7, 2011, at 1:11 PM, Gang-Ryung Uh wrote: > Hi, > > I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks, > > > > On Thu, Oct 6, 2011 at
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
Do you want to replace lui $2, %hi(g1) addiu $2, $2, %lo(g1) with this? la $2, g1 If that is the case, you can add this pattern. def op_la : Operand<i32>; def LA : FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), "la $dst, $addr0", [(set CPURegs:$dst, (add (MipsHi tglobaladdr:$addr0), (MipsLo tglobaladdr:$addr1)))], IIAlu>;
2014 Oct 01
2
[LLVMdev] LLVM opt GVN.cpp
Hi, I wonder what PRE algorithm is used for the GVN.cpp in LLVM. Any reference will be appreciated. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140930/3d7f74e3/attachment.html>
2011 Oct 06
1
[LLVMdev] MIPS 32bit code generation
Hi, for our micro-architecture research, we are using simplescalar 3.0 32bit mips simulator, which comes with binutils 1.5.2, and the ld fails at "lui" (bfd error). However, the ld is happy with "la" (assembler macro) and simulator correctly simulates. On Wed, Oct 5, 2011 at 5:04 PM, Eric Christopher <echristo at apple.com> wrote: > > On Oct 5, 2011, at 4:01 PM,
2011 Jul 15
2
[LLVMdev] LLVM and little-endian 32-bit MIPS code generation
Hi, We have tried and generate assembly code for very simple test C code. But, binutils-2.5.2 (simplesim-3.0) cannot handle the produced assembly code with the following complaints. Could you advise which version of bitutils that we need to use for mips code with LLVM with Clang? Thanks, $ GCC addr01.s addr01.s: Assembler messages: addr01.s:1: Error: Unknown pseudo-op: `.section'
2011 Jul 09
2
[LLVMdev] LLVM and little-endian 32-bit MIPS code generation
We are trying to use LLVM (Clang as the C frontend) to generate code for 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 sslittle-na-sstrix platform. Can you advise what would be the right way to use the LLVM compiler infrastructure? The following is the one I used, but it appears that it produce the code in big-endian (and I wonder whether the calling convention is right.) To
2011 Jul 11
0
[LLVMdev] LLVM and little-endian 32-bit MIPS code generation
It will produce little-endian code if you replace "mips" with "mipsel". 1. clang -ccc-host-triple mipsel-unknown-linux -ccc-clang-archs mipsel -O3 -S -emit-llvm foo.c -o foo.ll 2. llc -march=mipsel -mcpu=4ke foo.ll -o foo.s (the -march option is redundant) If you do not specify the target cpu with -mcpu, by default it will generate code for Mips1, which has not been tested as
2011 Jul 15
0
[LLVMdev] LLVM and little-endian 32-bit MIPS code generation
On Jul 15, 2011, at 10:13 AM, Gang-Ryung Uh wrote: > Hi, > > We have tried and generate assembly code for very simple test C code. But, binutils-2.5.2 (simplesim-3.0) cannot handle the produced assembly code with the following complaints. Could you advise which version of bitutils that we need to use for mips code with LLVM with Clang? Thanks, Something released in the last 10
2011 Oct 05
0
[LLVMdev] MIPS 32bit code generation
On Oct 5, 2011, at 4:01 PM, Gang-Ryung Uh wrote: > Hi, > > In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Why? -eric
2011 Jul 15
1
[LLVMdev] LLVM and little-endian 32-bit MIPS code generation
Hi, We would like to assemble .s file using binutils-2.5.2 which comes with simple-scalar3.0. Unfortunately, this particular version of binutils doesn't seem to handle global-offset-table (position independent code) and the some of the mips instructions. Thanks, On Fri, Jul 15, 2011 at 11:39 AM, Eric Christopher <echristo at apple.com>wrote: > > On Jul 15, 2011, at 10:13
2011 Jul 17
1
[LLVMdev] 32bit MIPS (little endian) code gen for simplescalar 3.0
We are using simplescalar 3.0 as an architecture simulation platform for our research. The current version of the simplescalar still uses gnu binutils 1.5. and gcc-2.7.2 to generate 32bit mips code. We are currently trying to replace gcc-2.7.2 by LLVM current. However, the generated code cannot be processed by this old binutils-1.5. We expect that it can be quite difficult to make simplescalar use
2010 Mar 16
0
[LLVMdev] how to configure llc to generate code for different architecture
Hi, Target architecture for llc can be specified using -march, -mcpu, -mattr options. Is it possible to override target CPU attributes when using llvm-gcc compiler? Regards, Sergey Y.
2013 Nov 28
2
derivar una función
Las dos Enviado desde mi iPhone > El 28/11/2013, a las 18:07, "Carlos J. Gil Bellosta " <cgb en datanalytics.com> escribió: > > ¿Numérica o simbólicamente? > > Un saludo, > > Carlos J. Gil Bellosta > http://www.datanalytics.com > > El día 28 de noviembre de 2013 18:03, jmcontreras <jmcontreras en ugr.es> escribió: >> Hola a todos
2010 Mar 16
5
[LLVMdev] how to configure llc to generate code for different architecture
Is it possible to configure llc to generate code for other architectures? For instance, what I need to do to generate Sparc machine code? Thanks. --Gang -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100316/253bd016/attachment.html>
2008 Sep 30
1
ordering problem
Hi there! I need some assistance here with vector orderings. I have a set of q vectors of length p, grouped by rows in a matrix A, q?p, that I need to order lexicographically (http://en.wikipedia.org/wiki/Lexicographical_order). I also have another matrix B, p?r, and a vector c, that should be ordered according to the order of A. So far, I was doing ordering <-
2007 Apr 06
4
Computing the rank of a matrix.
Hi! Maybe this is a silly question, but I need the column rank (http://en.wikipedia.org/wiki/Rank_matrix) of a matrix and R function 'rank()' only gives me the ordering of the elements of my matrix. How can I compute the column rank of a matrix? Is there not an R equivalent to Matlab's 'rank()'? I've been browsing for a time now and I can't find anything, so any
2008 Aug 28
3
Plots spanning columns
Hi! I want to plot three graphs (residuals, ACF and PACF of a model). Ideally I would use a c(2,2) disposition where the residuals plot would start at position 1,1 and span to position 1,2. Then I would plot the ACF in position 2,1 and the PACF in position 2,2. Maybe is clearer like this: -------------------------- | | | residuals | |