similar to: [LLVMdev] ASM output with JIT / codegen barriers

Responding to the original email... On Sun, Jan 3, 2010 at 10:10 PM, James Y Knight <foom at fuhm.net> wrote: > In working on an LLVM backend for SBCL (a lisp compiler), there are > certain sequences of code that must be atomic with regards to async > signals. Can you define exactly what 'atomic with regards to async signals' this entails? Your descriptions led me to think

On Jan 4, 2010, at 4:35 AM, Chandler Carruth wrote: > Responding to the original email... > > On Sun, Jan 3, 2010 at 10:10 PM, James Y Knight <foom at fuhm.net> wrote: >> In working on an LLVM backend for SBCL (a lisp compiler), there are >> certain sequences of code that must be atomic with regards to async >> signals. > > Can you define exactly what

On Mon, Jan 4, 2010 at 1:13 PM, James Y Knight <foom at fuhm.net> wrote: > Hi, thanks everyone for all the comments. I think maybe I wasn't clear that > I *only* care about atomicity w.r.t. a signal handler interruption in the > same thread, *not* across threads. Therefore, many of the problems of > cross-CPU atomicity are not relevant. The signal handler gets invoked via

On Jan 3, 2010, at 10:10 PM, James Y Knight wrote: > In working on an LLVM backend for SBCL (a lisp compiler), there are > certain sequences of code that must be atomic with regards to async > signals. So, for example, on x86, a single SUB on a memory location > should be used, not a load/sub/store sequence. LLVM's IR doesn't > currently have any way to express this

Hello, I have a question, what is wrong with the following code? declare void @llvm.memcpy.p0i64.p0i64.i8(i64*, i64*, i8, i32, i1) nounwind ... call void @llvm.memcpy.p0i64.p0i64.i8(i64* %19, i64* %21, i8 %17, i32 0, i1 false) ... According to the compiler this is the error, but I seem to miss where exactly my fault is. Intrinsic prototype has incorrect number of arguments! void (i64*,

On Mon, Jan 4, 2010 at 8:43 PM, Chandler Carruth <chandlerc at google.com> wrote: > On Mon, Jan 4, 2010 at 1:13 PM, James Y Knight <foom at fuhm.net> wrote: >> Hi, thanks everyone for all the comments. I think maybe I wasn't clear that >> I *only* care about atomicity w.r.t. a signal handler interruption in the >> same thread, *not* across threads. Therefore,

On Sep 7, 2010, at 8:03 AM, F van der Meeren wrote: > Hello, > > I have a question, what is wrong with the following code? > > declare void @llvm.memcpy.p0i64.p0i64.i8(i64*, i64*, i8, i32, i1) nounwind > > ... > > call void @llvm.memcpy.p0i64.p0i64.i8(i64* %19, i64* %21, i8 %17, i32 0, i1 false) > > ... > > > According to the compiler this is the

On Sep 7, 2010, at 8:03 AM, F van der Meeren wrote: > Hello, > > I have a question, what is wrong with the following code? > > declare void @llvm.memcpy.p0i64.p0i64.i8(i64*, i64*, i8, i32, i1) nounwind > > ... > > call void @llvm.memcpy.p0i64.p0i64.i8(i64* %19, i64* %21, i8 %17, i32 0, i1 false) > > ... > > > According to the compiler this is the

declare i8 @llvm.atomic.load.max.i8.p0i8( i8* <ptr>, i8 <delta> ) declare i16 @llvm.atomic.load.max.i16.p0i16( i16* <ptr>, i16 <delta> ) declare i32 @llvm.atomic.load.max.i32.p0i32( i32* <ptr>, i32 <delta> ) declare i64 @llvm.atomic.load.max.i64.p0i64( i64* <ptr>, i64 <delta> ) declare i8 @llvm.atomic.load.min.i8.p0i8( i8* <ptr>, i8

On Mon, Jan 4, 2010 at 8:51 PM, Jeffrey Yasskin <jyasskin at google.com> wrote: > On Mon, Jan 4, 2010 at 8:43 PM, Chandler Carruth <chandlerc at google.com> wrote: >> On Mon, Jan 4, 2010 at 1:13 PM, James Y Knight <foom at fuhm.net> wrote: >>> Hi, thanks everyone for all the comments. I think maybe I wasn't clear that >>> I *only* care about

On Mon, Jan 4, 2010 at 12:20 AM, Owen Anderson <resistor at mac.com> wrote: > > On Jan 3, 2010, at 10:10 PM, James Y Knight wrote: > >> In working on an LLVM backend for SBCL (a lisp compiler), there are >> certain sequences of code that must be atomic with regards to async >> signals. So, for example, on x86, a single SUB on a memory location >> should be

Hello, On the appended reasonably simple test case that has an fmul/fadd sequence on <8 x float> vector types, I don't see the x86-64 code generator (with cpu set to haswell or later types) turning it into an AVX2 FMA instructions. Here's the snippet in the output it generates: $ llc -O3 -mcpu=skylake --------------------- .LBB0_2: # =>This Inner

Hi All, I have a program that uses C++ STL a lot. To have the source code for STL functions, I undefined "_GLIBCXX_EXTERN_TEMPLATE" in c++config.h. In spite of this, after compilation (via clang) and linking (via llvm-ld), the resulting bitcode contains a few declared functions (with no definitions). My question is: In the scenario where some function definitions are missing in a llvm

See the bug for a reduction and the gimple trees. validate_arglist definately is rejecting the arglist in EmitBuiltinAlloca. (try: bool TreeToLLVM::EmitBuiltinAlloca(tree exp, Value *&Result) { tree arglist = TREE_OPERAND(exp, 1); if (!validate_arglist(arglist, INTEGER_TYPE, VOID_TYPE)) { debug_tree(arglist); return false; } Value *Amt = Emit(TREE_VALUE(arglist), 0); Amt =

On Feb 16, 2008, at 2:27 PM, Andrew Lenharth wrote: > See the bug for a reduction and the gimple trees. validate_arglist > definately is rejecting the arglist in EmitBuiltinAlloca. > > (try: > bool TreeToLLVM::EmitBuiltinAlloca(tree exp, Value *&Result) { > tree arglist = TREE_OPERAND(exp, 1); > if (!validate_arglist(arglist, INTEGER_TYPE, VOID_TYPE)) { >

On 2/16/08, Chris Lattner <sabre at nondot.org> wrote: > > This is very strange. I built a cross compiler to x86_64-unknown- > linux-gnu and it seems to work for me: > > ./cc1 /Users/sabre/pr1711.c -emit-llvm -quiet -O2 -o - > > target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32- >

Thanks Duncan and Ashok, As Duncan described, "lli -load=libstdc++.dylib ..." works. I, however, encounted an "Illegal instruction" message, while I was trying to interpret a large program. So, does lli have a debug switch for dumping out the details for errors? Using llc is not that simple, and I have not gotten through the compilation process. For instance, "llc -o

Guess I have found some clues. Some necessary libraries have to be loaded while trying to generate native code or do interpretation. Then another question emerges: Is there a way to determine the necessary libraries in need? And where to locate these necessary libraries? Xiaolong > Hi All, > > I have a program that uses C++ STL a lot. To have the source code for > STL functions, I

Hi, We seem to have found a bug in the LLVM 3.8 code generator. We are using MCJIT and have isolated working.ll and broken.ll after middle-end optimizations -- in the block merge128, notice that broken.ll has a fcmp une comparison to zero and a jump based on that branch: merge128: ; preds = %true71, %false72 %_rtB_724 = load %B_repro_T*, %B_repro_T**

Hi Xialong, > I have a program that uses C++ STL a lot. To have the source code for > STL functions, I undefined "_GLIBCXX_EXTERN_TEMPLATE" in > c++config.h. In spite of this, after compilation (via clang) and > linking (via llvm-ld), the resulting bitcode contains a few declared > functions (with no definitions). > > My question is: In the scenario where some