similar to: [LLVMdev] Tablegen & vector constants

I have two patterns in tablegen that do look like the exact same thing: Pat 1) def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst), (ins i16imm:$val), asm, [(set GPRV4I16:$dst, (build_vector (i16 imm:$val)))]>; Pat 2) def v4i16imm : Operand<v4i16>; def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst), (ins v4i16imm:$val), asm, [(set

Tom, There is no way to do this that I know of. Maybe David Greene or someone who hacks on Tablegen a lot would know. Micah > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Tom Stellard > Sent: Thursday, November 03, 2011 10:23 AM > To: LLVM Developers Mailing List > Subject: [LLVMdev] Tablegen:

I believe multiclasses can be nested. Could that help you reduce the duplication? --Sean Silva On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: > > multiclass

Hi, I'm working on an LLVM backend for GPUs. One thing that is a little different about some GPUs is that instructions can take registers or 32-bit floating point immediates as arguments. I was wondering if there is a way to model this using tablegen, without having to define an instruction for each possible combination of registers and immediates (e.g. For ADD it would require four

On Wed, Jun 20, 2012 at 3:40 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Possible to add a test case? I am not really sure what I would check. At first, I thought to add a testcase to test/TableGen; as this patch does not modify tablegen, it doesn't make sense. What kind of test should I write for this? The test should be a tablegen file that includes

That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: multiclass instmcRegImm<...> { def rr: inst<...>; def ri: inst<...>; def ir: inst<...>; def ii: inst<...>; } multiclass instmc<...> { defm i8 : instmcRegImm<...>; ^-- repeat for 15

I think a multiclass may be a better fit for what you are trying to do. In fact, this is the canonical example for multiclasses: <http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-and-instances>. --Sean Silva On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I’m trying to find examples of the foreach pattern being used in

I still think there is a bug somewhere, but not sure where yet. This is what is generated in intrinsic.gen: case Intrinsic::opencl_math_fdistance: // llvm.opencl.math.fdistance ResultTy = Type::FloatTy; ArgTys.push_back(Tys[0]); ArgTys.push_back(Tys[0]); break; This is the intrinsic definition: def int_opencl_math_fdistance_fast : Intrinsic<[llvm_float_ty],

> -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: Monday, November 08, 2010 10:41 AM > To: Villmow, Micah > Cc: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Creating tablegen patterns for intrinsics with > no return value. > > > On Nov 8, 2010, at 10:32 AM, Villmow, Micah wrote: > > > I have intrinsic with no

On Wed, Apr 15, 2009 at 11:15 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I still think there is a bug somewhere, but not sure where yet. > This is what is generated in intrinsic.gen: > case Intrinsic::opencl_math_fdistance:          // > llvm.opencl.math.fdistance >    ResultTy = Type::FloatTy; >    ArgTys.push_back(Tys[0]); >    ArgTys.push_back(Tys[0]);

On Mon, Sep 15, 2008 at 4:51 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > With my backend code gen I want to assign calling parameters to a list of > registers, but since I'm targeting a virtual instruction set. I don't want > to be limited by the number of registers. Is there a way using TableGen to > specify just a starting register to assign to for the

Hi Micah, On Tue, Jun 25, 2013 at 03:47:14PM +0000, Micah Villmow wrote: > How do you specify in a tablegen pattern that all destination registers are also source registers? I know I could just duplicate them, but I was wondering if there was a way it could be done without doing this. Basically an inplace operation. > I'm not sure if there is a good way to do this. The

Possible to add a test case? Micah > -----Original Message----- > From: Sebastian Pop [mailto:spop at codeaurora.org] > Sent: Wednesday, June 20, 2012 1:40 PM > To: Villmow, Micah > Cc: llvmdev at cs.uiuc.edu; llvm-commits at cs.uiuc.edu > Subject: Re: [LLVMdev] How to define macros in a tablegen file? > > On Wed, Jun 20, 2012 at 12:34 PM, Sebastian Pop <spop at

If I force it to use v2f32 for my register class, it still fails with: d:\hq\main\sw\appeng\tools\hpc\opencl\compiler\llvm\test\AMDIL>TableGen. exe -gen -dag-isel -I../../include/ test.td > output GPRV2F32:v2f32:$src1 MACRO_DISTANCE_FAST_v2f32: (set GPRF32:f32:$dst, (i ntrinsic_w_chain:f32 84:iPTR, GPRV2F32:v2f32:$src0, GPRV2F32:v2f32:$src1)) TableGen.exe: In

Right, it's failing when it tries to materialize a move of a constant into a register. But it's only trying to do that because it previously failed to fold the constant into the AND. What you need to do is step through the path it takes when matching the AND node, and try to figure out why it ends up selecting the register-register version rather than the register-immediate version.

Sebastian, If not a test, how about a patch in the documentation for TableGen about this new feature that you're making available? -- Evandro Menezes Austin, TX emenezes at codeaurora.org Qualcomm Innovation Center, Inc is a member of the Code Aurora Forum On 06/20/12 16:02, Sebastian Pop wrote: > On Wed, Jun 20, 2012 at 3:40 PM, Villmow, Micah<Micah.Villmow at

Why not just run the c preprocessor before running tablegen? Micah > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Jeroen Dobbelaere > Sent: Wednesday, August 07, 2013 1:33 AM > To: llvmdev at cs.uiuc.edu > Subject: [LLVMdev] tablegen question > > Hi, > > I am trying to make my tablegen

I'm trying to find examples of the foreach pattern being used in tablegen files. The problem I am trying to solve is to simplify the amount of tablegen code I have to produce because each operand of an instruction can be a register or a literal. So for binary, we have 4 instructions, ternary, 8, and quaternary 16 combinations. Instead of writing all the combinations out, I'd like to use

Micah, One more thing ;) -- llvm::getEnumName in utils/TableGen/CodeGenTarget.cpp -Hal On Tue, 31 Jul 2012 21:02:02 +0000 "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > Ahh yep, thanks for catching that, new patch attached. > > > -----Original Message----- > > From: Hal Finkel [mailto:hfinkel at anl.gov] > > Sent: Tuesday, July 31, 2012 1:40 PM

That's how ISD::SETCC is specified. If you want to change that for your target, you should custom lower these nodes to target nodes. Then you can specify your own SDNode with your own SDTypeProfile. Evan On Oct 24, 2008, at 4:31 PM, Villmow, Micah wrote: > I am attempting to match setcc using tablegen w/ the following > patterns: > def FEQ : Instruction<(outs