similar to: [LLVMdev] SubclassData in SDNode

On Jul 31, 2009, at 11:26 AM, David Greene wrote: > Right now the MemSDNode keeps a volatile bit in the SubclassData to > mark > volatile memory operations. > > We have some changes we'd like to push back that adds a NonTemporal > flag > to MemSDNode to mark instructions where movnt (on x86) and other > goodness > can happen (we'll also add the TableGen

I also want a way to add target specific flag to a SDNode (which should be transferred to MachineInstr). For example, on x86 lots of opcodes have *lock* variants. Right now, these are separate instructions. I'd prefer to make it into a target specific flag that can be toggled by some sort of post-isel action routine. One way to handle this might be to expand the use of SubclassData.

On Sunday 02 August 2009 20:57, Evan Cheng wrote: > I also want a way to add target specific flag to a SDNode (which > should be transferred to MachineInstr). For example, on x86 lots of > opcodes have *lock* variants. Right now, these are separate > instructions. I'd prefer to make it into a target specific flag that > can be toggled by some sort of post-isel action routine.

On Saturday 01 August 2009 15:12, Dan Gohman wrote: > LoadSDNode, which inherits from MemSDNode is the largest > SDNode. With the current SDNode allocation strategy, making it > bigger will increase the allocation needed for all nodes. Ok. > > new (N) LoadSDNode(..., isVolatile|isNonTemporal); > > > > Thoughts? > > This sounds reasonable. I'd suggest

On Aug 3, 2009, at 9:30 AM, David Greene wrote: > On Saturday 01 August 2009 15:12, Dan Gohman wrote: > >> LoadSDNode, which inherits from MemSDNode is the largest >> SDNode. With the current SDNode allocation strategy, making it >> bigger will increase the allocation needed for all nodes. > > Ok. > > >>> new (N) LoadSDNode(...,

Hello Ether, I think it is referring to the Value class (captial V) whose documentation is found at http://llvm.org/doxygen/classllvm_1_1Value.html . It has to be a pointer because the Value class is a parent class to many many child classes. --Sam ----- Original Message ---- > From: ether zhhb <etherzhhb at gmail.com> > To: LLVM Developers Mailing List <llvmdev at

hi, i am building selectionDAG by my own code, but got a assertion fail said "SrcValue is not a pointer?". but since the comment above the SrcValueSDNode said: "SrcValueSDNode - An SDNode that holds an arbitrary LLVM IR Value." why the llvm value of SrcValueSDNode must be with PointerType? is that assertion necessary? thanks a lots. regards --ether

Right now the MemSDNode keeps a volatile bit in the SubclassData to mark volatile memory operations. We have some changes we'd like to push back that adds a NonTemporal flag to MemSDNode to mark instructions where movnt (on x86) and other goodness can happen (we'll also add the TableGen patterns to properly select movnt). In our tree we simply added another flag to the MemSDNode

hi Eli, thanks for reply :) i am currently decompose the BR_CC node to a target SETCC node and a target BRCOND node, but since BR_CC node sometimes is combine from a BRCOND node and SETCC node, so i just wondering if theres any better way :) regards --ether

Hello devs, Recently I've been working on a bug that can probably be fixed with the addition of a simple flag to a class descendant of `llvm::Value`. Without increasing the size of the class, I can just add this flag to `llvm::Value::SubclassData`. But this is not an easy task! This is because the offsetes/sizes of the data stored in the `SubclassData`, are hardcoded literals/enums. If you

I've tested it on MSVC, gcc, clang and icc. The solution in clang (in Decl.h) is not ideal (as you have said yourself). The solution I offer, is using a union of fields of class BitField (this is a new class that implements a bitfield of a specific type requested). With this, the definition, of the required bitfields in the subclass data, remains in the hands of the actual class needing them.

Here is the patch 0004-Enable-HLE-code-generation.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. > To

Here is the patch 0002-Add-HLE-target-feature.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and XRELEASE prefixes. > To support

Here is the patch 0003-Add-XACQ-XREL-prefix-and-encoding-asm-printer-suppor.patch Yours - Michael On Tue, 2013-02-19 at 14:07 -0800, Michael Liao wrote: > Hi All, > > I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. > HLE from Intel TSX [2] is legacy compatible instruction set extension to > specify transactional region by adding XACQUIRE and

Hi Michael, Why do you want to add transactional memory support to LLVM ? Can't you implement transactional memory using a library call ? Judging by the number of patches it looks like a major change to LLVM, and I am not sure that I understand the motivation for including it in LLVM. Thanks, Nadav On Feb 19, 2013, at 11:52 AM, Michael Liao <michael.liao at intel.com> wrote:

hi again :) On Tue, Apr 13, 2010 at 8:57 AM, ether zhhb <etherzhhb at gmail.com> wrote: > hi john, > > thanks very much, i will try it out. > > --best regards > ether > > > On Mon, Apr 12, 2010 at 10:03 PM, John Criswell <criswell at uiuc.edu> wrote: > >> ether zhhb wrote: >> >>> hi all, >>> >>> i have some thing

Nadav, I've been reading over the patches and I was wondering if you could elaborate your concerns here. I share your goal of reducing compilation time regressions for users that don't care about new feature X. From my very quick glance over the patches, I didn't see anything I couldn't opt out of. Maybe we can talk about specifics and figure out a way to make these changes not

Hi All, I'd like to add HLE support in LLVM/clang consistent to GCC's style [1]. HLE from Intel TSX [2] is legacy compatible instruction set extension to specify transactional region by adding XACQUIRE and XRELEASE prefixes. To support that, GCC chooses the approach by extending the memory order flag in __atomic_* builtins with target-specific memory model in high bits (bit 31-16 for

Hi Ether, The detection for graphviz / dotty / ... has been added recently to llvm cmake. It should work properly if those tools are available in the PATH. The related svn commits are : 86153, 86547 and 86644. Those commits are not present in llvm release <= 2.6, but they are straight forward to apply. Best regards, -- Arnaud de Grandmaison -----Original Message----- From: llvmdev-bounces at

Hi Ether, I work under Windows and am able to view graphs generated by LLVM. I haven't tried generating and viewing dog graphs while debugging but I hope this helps. What I do is to invoke llc.exe and pass a switch to generate the graph at the stage(s) you want to see (DAG combine, legalize, scheduling, etc), for example: llc.exe mykernel.ll -view-legalize-dags -f. The graphs are saved