similar to: [LLVMdev] Unsigned int multiplication using UMUL_LOHI

On Wed, May 20, 2009 at 5:26 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: >> Can you explain why you chose the approach of using a new pass? >> I pictured removing LegalizeDAG's type legalization code would >> mostly consist of finding all the places that use TLI.getTypeAction

Hey, I’ve been working on custom lowering ISD::UMUL_LOHI and ISD::SMUL_LOHI. Our target has some legal vector types but no support for these so would like to mark them as Expand. This yields “Cannot unroll a vector with multiple results!” from the default case in VectorLegalizer::Expand. Hence custom lowering. All the types are legal at this stage. I would appreciate some clarification on

I've been working on a backend for a 16-bit microcontroller and I've just updated my base from LLVM 3.4 to LLVM 3.5.0. This threw up a regression failure in my test suite, and having tracked down the cause, I'm now confused about the DAG legalization and optimization process which I thought I understood. I'd be really grateful for advice on whether I've misunderstood how

Thanks Eli. I didn't know that the operand sign didn't affect the operation as I've never done multiplication at the bit level. Javier On Tue, 8 Dec 2009 20:16:23 -0800, Eli Friedman <eli.friedman at gmail.com> wrote: > On Tue, Dec 8, 2009 at 7:16 PM, Javier Martinez <javier at jmartinez.org> > wrote: >> Eli, >> >> I think it is an error for LLVM

I'm trying to implement *MUL_LOHI for my processor. My processor has mulxss (e.g.) that gives the 32 high bits of a 64 bit multiply. I tried this in ios2ISelDAGToDAG.cpp: /// Mul/Div with two results case ISD::SMUL_LOHI: case ISD::UMUL_LOHI: { SDValue Op1 = Node->getOperand(0); SDValue Op2 = Node->getOperand(1); AddToISelQueue(Op1);

Hi, When expanding multiply operation in LegalizeTypes LLVM generates some nodes such as UMUL_LOHI (please refer file LegalizeIntegerTypes.cpp - function - ExpandIntegerResult). However while lowering this operation in LegalizeDAG (please refer file LegalizeDAG.cpp - function - LegalizeOp) the comment says "These nodes will only be produced by target-specific lowering.....".

Thanks Dylan, I am working on a backend which has mulhsu instruction that performs multiplication between signed and unsigned number and returns upper 32 bits into result register. I think I also need to write some code probably as you indicated to check signedness of the operands and based on that lower to mulhsu instruction. -Vivek On Mon, Feb 27, 2017 at 11:13 AM, Dylan McKay <me at

>>Note that the isCommutable flag is only really useful for two-address instructions. If the two inputs are not constrained, nothing is really won by swapping them. Ahh i see, good to know that. >> Does the -view-*-dags output look correct? They do look correct, there are three Xmul_lohi blocks, one returns the low part copied into R14 and the rest of combinations get added and merged

Hi Christophe, On 05/09/11 18:35, Christophe de Dinechin wrote: > > On 5 sept. 2011, at 17:48, Duncan Sands wrote: > >> since the result of a multiply doesn't depend on the signedness, I find it >> strange that your target differentiates between them. What I'm saying is >> that if you have (say) two i32 numbers a and b and you do a signed multiply: >>

On Wed, Dec 17, 2008 at 11:49 PM, <Sachin.Punyani at microchip.com> wrote: > 2) Why is custom legalization of this node not allowed? No target has needed it so far. Why do you need it? > 3) My target does not have any instruction directly matching to this > operation. How should this node be legalized? If your target doesn't have this operation, you should mark

Hi all, While I test "clang-tests/gcc-4_2-testsuite/src/gcc.c-torture/execute/20020226-1.c", I faced something wrong with "DAGCombiner::MatchRotate" function. This function tries to consume some patterns and generate "ROTL" or "ROTR" dag node as following comments: "DAGCombier::MatchRotate" function in DAGCombiner.cpp Pattern1 // fold (or

On 2008-09-29 07:46, Keun Soo Yim wrote: > Does anyone succeed at compiling Linux kernel for Sparc v8 architecture? > I am currently trying to expand the regime of LLVM to Sparc kernel codes. > The following is the initial error messages. Any comment is welcomed. > > #1. Inline Assembly > > > > Code: > > register struct thread_info

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

Eli Friedman wrote: > I haven't looked at the rest of the email carefully, but why aren't > you just implementing MULHU and MULHS? There's no point to > implementing the *MUL_LOHI variants if the processor doesn't have > them. I have implemented MULHU and MULHS. But if I take out my *MUL_LOHI stuff, the error I get is [~/ellcc/ellcc] main% ./nios2-elf-ecc -S test.c

Hi Gabrielle, > > Historically nodes marked "custom" were considered legal, so the > > DAGCombiner would have been correct to generate it. Not sure how > > that ever worked though. I think Dan split the isOperationLegal > > method into isOperationLegal and isOperationLegalOrCustom for reasons > > related to this kind of thing. I don't know whether

I found a bug in the expansion code for SUB going back to at least LLVM 2.6 and still shows up in trunk. case ISD::SUB: { EVT VT = Node->getValueType(0); assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && TLI.isOperationLegalOrCustom(ISD::XOR, VT) && "Don't know how to expand this subtraction!"); Tmp1 = DAG.getNode(ISD::XOR, dl,

On May 21, 2012, at 11:21 AM, Villmow, Micah wrote: > I found a bug in the expansion code for SUB going back to at least LLVM 2.6 and still shows up in trunk. > case ISD::SUB: { > EVT VT = Node->getValueType(0); > assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && > TLI.isOperationLegalOrCustom(ISD::XOR, VT) && > "Don't

Richard Pennington wrote: > Eli Friedman wrote: > >> I haven't looked at the rest of the email carefully, but why aren't >> you just implementing MULHU and MULHS? There's no point to >> implementing the *MUL_LOHI variants if the processor doesn't have >> them. >> > > I have implemented MULHU and MULHS. But if I take out my

> Historically nodes marked "custom" were considered legal, so the > DAGCombiner would have been correct to generate it. Not sure how > that ever worked though. I think Dan split the isOperationLegal > method into isOperationLegal and isOperationLegalOrCustom for reasons > related to this kind of thing. I don't know whether the DAGCombiner > is now only supposed