similar to: [LLVMdev] hi, Hi, (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really?

On Dec 3, 2009, at 9:52 PM, 任坤 wrote: > I am travelling CFG with MachineFunction. So I want to sure it. > (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really? If the CFG contains loops, how could this be possible? Anyway, no you can't use MBB numbers for that. Perhaps you need the MachineDominatorTree analysis? Regards, /jakob

On Dec 3, 2009, at 9:52 PM, 任坤 wrote: > Hi, EveryOne: > > I am travelling CFG with MachineFunction. So I want to sure it. > (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really? > Hi 任坤, I can't say for sure, though I don't think we make assurances that this is the case. If you want to traverse the CFG, there should

hi, Dear Evan Cheng: My cpu is i32 embeded CPU. I define pseudo register pair registers. In mytargetRegisterInfo.td: def T0: RegisterWithSubRegs<"t0",[R0,R1]>; ... def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] In mytargetISelLowering.cpp: I define i1, i8 , i16 and i32 are legal. 1. I still have problem. I save my function return double  value in

Dear Evan Chang: I register incorrect Register class for MVT::f64. I have fixed it. Thanks your advice. "-view-legalize-dags" is very good option. But I don't know why my LLC do not know " -view-legalize-type-dags" option. By the way, I use llvm 2.5 merged from llvm2.4. Best Regards, Ren Kun --- 09年3月31日，周二, Evan Cheng <echeng at apple.com> 写道： 发件人: Evan Cheng

I try to define a register class def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] to simulate even/odd pair of GPR32 register. Actually, I just use GPR64 as a temporary register. My CPU just support i32 Integer type directly. I use FDR to save f64. def FDR : RegisterClass<"mytarget", [f64], 64,[FD0, FD1, ....] When I move f64 to even/odd pair register, I

On Feb 19, 2009, at 8:26 PM, 任坤 wrote: > hi, Dear Evan Cheng: > > My cpu is i32 embeded CPU. I define pseudo register pair registers. > > In mytargetRegisterInfo.td: > def T0: RegisterWithSubRegs<"t0",[R0,R1]>; > ... > def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] > > In mytargetISelLowering.cpp: > I define i1, i8 ,

Hi: I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks. 1. MachineDominatorTree *domintree = new MachineDominatorTree(); domintree->runOnMachineFunction(mf); 2. Then travel mf one by one. When domintree->dominates(next,current) is true, there is a backedge from current node to next node. move this backedge form CFG. But I find A LOOP in

2010/1/25 任坤 <hbrenkun at yahoo.cn>: > Hi: > > I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks. > > 1. MachineDominatorTree *domintree = new MachineDominatorTree(); > domintree->runOnMachineFunction(mf); > > 2. Then travel mf one by one. > When domintree->dominates(next,current) is true, there is a backedge

Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's

On Jan 14, 2010, at 6:39 PM, 任坤 wrote: > But I want do some optimization after register alloction by adjusting > register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. You can also look at RegisterScavenging.cpp and MachineVerifier.cpp. They are doing the same

Hi, Dear Boissinot: 1. When I have irreducible CFG, I travel its nodes by DFS. search backedge for every node. After I finish one node, push it into a stack. [0, 1, 2, M] <---push. [0, 1, 2, M,...N] <---push. When resolving node M, find a edge from node N to node M, N is not in stack(M < N), It is a backedge. N is in stack(M > N), It is NOT a backedge.

Hi:    I want to do some optimization on MachineLoop. So I want to get MachineLoopInfo from MachineFunction. I reference MachineLICM.cpp. So I try to write a pass in Target/mytarget directory. I find there is Error. llvm/include/llvm/PassAnalysisSupport.h:198: AnalysisType& llvm::Pass::getAnalysisID(const llvm::PassInfo*) const [with AnalysisType = llvm::MachineLoopInfo]: Assertion

I am porting llvm-gcc frontend. We have ported GCC4.2 for our target. So I move *.h *.md and *.c to llvm-gcc.  I do not implement any LLVM MACRO, and use default action of llvm-gcc.  I get a new llvm-gcc for our target. But I get a bug. /******************************/ //#include <stdio.h> union MYunion {   unsigned char uc ;   int ui; } myunion; void vfu1(union MYunion  u) {     u.ui =

hi,      I am porting llvm to our embedded cpu. By my abi, long long type is aligned by 8 bytes. But now llvm-gcc frontend follows x86 abi, generate word-alignment LLVM-IR for va_arg().    In some degree, llvm-gcc frontend depends on targets. The best solution is llvm-gcc can create va_arg node, I can lower it at the backend.    Who can give a temporary solution to make frontend can create 8

I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr. But I need to use an even/odd register pair to save its 2 operands. I define in mytarget.td: myfmdrr: SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,     SDTCisSameAs<1, 2>]>; def my_fmdrr : ........... def myFMDRR : ....                       (outs FPR: $result), ins(GPR:

Hi 任坤, > void vfu1(union MYunion u) { > u.ui = 99; > } here u is passed by copy, so vfu1 has no externally visible effect. I think you meant: union MYunion *u > define void @vfu1(%struct.MYunion* byval align 4 %u) nounwind { Here "byval" means that a pointer to a temporary copy of u is being passed, not u itself. Thus any writes to the %u parameter have no effect

Hi: I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks. 1. MachineDominatorTree *domintree = new MachineDominatorTree(); domintree->runOnMachineFunction(mf); 2. Then travel mf one by one. When domintree->dominates(next,current) is true, there is a backedge from current node to next node. move this backedge form CFG. But I find A LOOP in

Hi, I am working with regular dominator tree and not MachineDominatorTree. I wanted to modify the CFG structure and for that I need to change successor of a basic block. How can I do that? Or is there a way to cast a BasicBlock to MachineBasicBlock so that i can use functions addSucessor and removeSuccessor for the basic block. It will be great if someone can help. regards, Ambika

Thank you, Nick. Yes, I have add getAnalysisUsage. As I know, some CFG is irreducible. At this time, Dominator Tree can not find some backedge. Is it means some MachineLoop is not be found? dominatorTree.jpg is a previous exmaple. best regards! renkun --- 10年3月9日，周二, Nick Lewycky <nicholas at mxc.ca> 写道： > 发件人: Nick Lewycky <nicholas at mxc.ca> > 主题: Re: [LLVMdev] Find

I'm looking for a way to traverse machine basic blocks in a specific order. Basically I want all blocks that are predecessors to the current block to be traversed before the current block. I've looked at MachineDominatorTree but this doesn't traverse them in quite the way I want them to. Anyone know of a way to do this? Thanks, Micah -------------- next part -------------- An HTML