Displaying 20 results from an estimated 2000 matches similar to: "[LLVMdev] windows build"
2009 Oct 28
2
[LLVMdev] windows build
done
http://llvm.org/bugs/show_bug.cgi?id=5331
shrey
On Wed, Oct 28, 2009 at 3:29 PM, Óscar Fuentes <ofv at wanadoo.es> wrote:
> shreyas krishnan <shreyas76 at gmail.com> writes:
>
>> I am running into bunch of windows build issues. Can someone
>> please provide help on what might be going wrong
>>
>>
>>
2009 Oct 28
0
[LLVMdev] windows build
shreyas krishnan <shreyas76 at gmail.com> writes:
> I am running into bunch of windows build issues. Can someone
> please provide help on what might be going wrong
>
>
> llvm\win32\Configure\..\llvm\ADT\hash_set.h
> 1>The system cannot find the file specified.
>
> Similarly
> 2>c1xx : fatal error C1083: Cannot open source file:
>
2009 Oct 30
0
[LLVMdev] windows build
thanks for the help ..I could build it with cmake generated project files
Being a newbie with cmake one question, is it equivalent to configure
in windows environment and so would need to be run everytime I change
the source location ?
thanks
shrey
On Wed, Oct 28, 2009 at 4:31 PM, shreyas krishnan <shreyas76 at gmail.com> wrote:
> done
>
>
2009 Jul 16
3
[LLVMdev] registers as home location
Hi
As part of a requirement that I have, I would like to have some
globals reside in registers always. So these variables would not have
a home location in memory.
I realize the code generated would also need to be aware of this. I do
have some ideas on how to change the code appropriately. But right
now, I am more concerned about how to fit this requirement (sort of
interprocedural) into the
2015 May 14
4
[LLVMdev] getnode(BB) = 0; block already in dominator tree
Hi
I run into an issue as part of splitting a critical edge during LICM.
When a new basic block is created and needs to be added into the dominator
tree, the block is already in the dominator tree. I print the dominator
tree and I see it is added into the tree as child of node it is supposed to
dominate.
How do I debug to find out why/when its getting added into the tree. ?
Tips/suggestions on
2010 Jul 17
2
[LLVMdev] v16i32/v16f32
I tried adding them in my backend however I run into the assertion
assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
ExtType < array_lengthof(LoadExtActions) &&
"Table isn't big enough!");
What does the assertion mean ?
thanks for all help!!
shrey
On Wed, Jul 14, 2010 at 6:56 PM, Eli Friedman <eli.friedman at
2010 Jul 15
2
[LLVMdev] v16i32/v16f32
Hi
I find types such as v16i32, v16f32 missing in my llvm version 2.7
So does the following page not list them
http://llvm.org/docs/doxygen/html/classllvm_1_1MVT.html
is that intentional for any reason or can I just add them ?
thanks
shrey
2009 Nov 17
3
[LLVMdev] windows build
Hi all
I am building LLVM 2.6 on VC++. I am running into this problem
where even builds without any changes whatsoever causes rebuilding of
certain directories like table gen of intrinsics and x86 target files.
This then leads to build of the x86 codegen. Is this expected ? Any
pointers to how I can avoid this?
thanks
shrey
2009 Jul 16
2
[LLVMdev] registers as home location
Thanks Eli, Jaffrey for the pointer!
A couple of further questions if I may
1. Isnt this assuming that register being pinned to is always esi when
it comes to using a calling convention.
I would like to pin the register through a pass and so I dont know
which registers ends up being used for a particular value before hand
2. I would also like to allocate some small aggregates into registers.
I
2011 Aug 14
1
[LLVMdev] associating id with opcodes
I am sorry, I actually meant Machine Instructions - is there a way ?
One use of that is I would like to be able to group instructions
together and be able check their group quickly.
thanks
shrey
On Sun, Aug 14, 2011 at 1:16 AM, Bill Wendling <wendling at apple.com> wrote:
> On Aug 13, 2011, at 11:04 AM, shreyas krishnan wrote:
>
>> Hi
>> Is there a way to associate
2012 Oct 10
2
[LLVMdev] Order of values
Hi
if I have group of instructions that belong to same basic block,
how can I determine which of these occurs the last ?
thanks
Shrey
2009 Jul 16
0
[LLVMdev] registers as home location
Chris recently wrote up a way to do this at
http://nondot.org/sabre/LLVMNotes/GlobalRegisterVariables.txt
On Thu, Jul 16, 2009 at 1:53 PM, shreyas krishnan<shreyas76 at gmail.com> wrote:
> Hi
> As part of a requirement that I have, I would like to have some
> globals reside in registers always. So these variables would not have
> a home location in memory.
> I realize the
2009 Nov 13
3
[LLVMdev] legalize dag problem
Hi
I am running into a legalize dag issue after custom lowering a
load. If someone can give me pointers that would be great. I am using
llvm 2.6
When custom lowering a load, the following code gets executed.
Tmp1 = TLI.LowerOperation(Tmp3, DAG);
if (Tmp1.getNode()) {
Tmp3 = LegalizeOp(Tmp1);
Tmp4 = LegalizeOp(Tmp1.getValue(1)); <----------------- what
2009 Jul 16
0
[LLVMdev] registers as home location
On Thu, Jul 16, 2009 at 2:41 PM, shreyas krishnan<shreyas76 at gmail.com> wrote:
> Thanks Eli, Jaffrey for the pointer!
>
> A couple of further questions if I may
> 1. Isnt this assuming that register being pinned to is always esi when
> it comes to using a calling convention.
You'd need a separate calling convention for each possible set of
registers pinned. The
2010 Jul 15
0
[LLVMdev] v16i32/v16f32
On Wed, Jul 14, 2010 at 6:48 PM, shreyas krishnan <shreyas76 at gmail.com> wrote:
> Hi
> I find types such as v16i32, v16f32 missing in my llvm version 2.7
>
> So does the following page not list them
> http://llvm.org/docs/doxygen/html/classllvm_1_1MVT.html
>
> is that intentional for any reason or can I just add them ?
As far as I know, they're not there
2010 Jul 17
0
[LLVMdev] v16i32/v16f32
On Fri, Jul 16, 2010 at 5:14 PM, shreyas krishnan <shreyas76 at gmail.com> wrote:
> I tried adding them in my backend however I run into the assertion
>
> assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
> ExtType < array_lengthof(LoadExtActions) &&
> "Table isn't big enough!");
>
> What does the
2009 Aug 31
1
[LLVMdev] machine ir transformation
Hi
I would like to add transformation - mostly peephole- after
register allocation that make use of def-use information. Would it be
possible to make use of the dag codebase to help do that ?
thanks for any pointers
shrey
2009 Nov 13
1
[LLVMdev] legalize dag problem
thanks for the help ..I do add the chain and the result.
My code is like this ...
SDValue Ops[] = { load->getChain(), load->getOperand(1),
load->getBasePtr(), des };
DAG.getNode(CustomOpc, NodeTys, Ops, 4);
thanks again!
shrey
On Thu, Nov 12, 2009 at 4:41 PM, Anton Korobeynikov
<anton at korobeynikov.info> wrote:
>> My problem is that the second call asserts inside
2009 Dec 11
1
[LLVMdev] machine register info
hi
I find machine register info carrying the lists of def use for
each register - PhysRegUseDefLists[RegNo];. I dont see a lot of places
using this. For instance, if this list is accurate, can this be used
for def use relationships at different points?
thanks
shrey
2013 May 03
1
[LLVMdev] slotindex:getIndex
HI
Is there a public function equivalent of calling getIndex I would
like to use some sort of starting slot info of a live interval in some
pass. I need a way of comparing which virtual register is associated
with an earlier source line without relying on any debug info. The
relative order is preserved in my case.
thanks
shrey