similar to: [LLVMdev] arm cortex-m3

Here is a one-line patch to support the cortex-m3. For those who plan the features for ARM, the new cortex-m0 implements only a subset of the Thumb2 instructions. I still have yet to see a document that details what's in the subset. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: arm.diff URL:

Looks OK to me, but I don't have any Cortex-M3 docs to confirm the choice of v7-A without NEON. deep On Sun, Nov 22, 2009 at 9:47 PM, Bagel <bagel99 at gmail.com> wrote: > Here is a one-line patch to support the cortex-m3. > For those who plan the features for ARM, the new cortex-m0 implements only a > subset of the Thumb2 instructions.  I still have yet to see a document that

On 23 July 2012 17:03, Chris Cadwallader <ccadwallader at arxan.com> wrote: > On Darwin, if -march is armv7 clang's driver will assume you want thumb2 unless you also give it -mno-thumb but that is irrelevant with mcpu=cortex-m3. I think that Thumb2 should be the default for v7 on any system, not just Darwin. Maybe some ARM folk can comment on this... -- cheers, --renato

Is anyone working on supporting additional targets used in embedded systems. I am particularly interested in two: 1. TI MSP430. http://en.wikipedia.org/wiki/TI_MSP430 A nice very low power 16-bit machine with a PDP-11-like instruction set. We can assume the PIC16 developers have found and fixed all the 32-bit assumptions in the code base. Newer versions, the MSP430X series, have

On Darwin, if -march is armv7 clang's driver will assume you want thumb2 unless you also give it -mno-thumb but that is irrelevant with mcpu=cortex-m3. I agree its a mess. -Chris On Jul 22, 2012, at 4:37 PM, Renato Golin wrote: > On 22 July 2012 20:42, Anton Korobeynikov <anton at korobeynikov.info> wrote: >>> Any suggestions? >> Try to specify CPU explicitly. >

On Mon, Jul 23, 2012 at 8:14 PM, Renato Golin <rengolin at systemcall.org> wrote: > On 23 July 2012 17:03, Chris Cadwallader <ccadwallader at arxan.com> wrote: >> On Darwin, if -march is armv7 clang's driver will assume you want thumb2 unless you also give it -mno-thumb but that is irrelevant with mcpu=cortex-m3. > > I think that Thumb2 should be the default for v7

Assume an architecture that has multiple condition code registers, e.g., powerpc. Now assume that there are predicate instructions like thumb2, but can specify which condition code register they refer to. Now also assume that these predicate instructions themselves are predicatible, if executed they change the current predication state. Can LLVM handle multiple levels of predication? When is

I am writing a backend for an experimental machine that has both 2-address and 3-address versions of some instructions. The 2-address versions are more compact and thus preferred when applicable. How does one go about generating the most compact version? 1. At instruction selection, is there a predicate that can test whether one of the input sources is dead, thus allowing the selection of the

On Jul 23, 2012, at 1:52 PM, salvatore benedetto <salvatore.benedetto at gmail.com> wrote: > On Mon, Jul 23, 2012 at 8:14 PM, Renato Golin <rengolin at systemcall.org> wrote: >> On 23 July 2012 17:03, Chris Cadwallader <ccadwallader at arxan.com> wrote: >>> On Darwin, if -march is armv7 clang's driver will assume you want thumb2 unless you also give it

Hi, I am trying to cross compile code for ARM Cortex m0, m3, and m4. For m0, I use: -target armv6--eabi -mcpu=cortex-m0 That seems to work. For m3 and m4, I use the following which does not work (fatal error: error in backend: CPU: 'cortex-m3' does not support ARM mode): -target armv7m--eabi -mcpu=cortex-m3 and -target armv7em--eabi -mcpu=cortex-m4 Who can help me with the

The thumb2 instructions include unsigned and signed divide. Attached are a patch and test routine. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: div.diff URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091201/675cf4c5/attachment.ksh> -------------- next part -------------- An embedded and charset-unspecified text was

On 22 July 2012 20:42, Anton Korobeynikov <anton at korobeynikov.info> wrote: >> Any suggestions? > Try to specify CPU explicitly. He shouldn't have to, but that might help. Maybe setting -march? This is a big mess... I thought that v7 always assumed Thumb2 for the thumb flag, and v7M should always assume Cortex-M3 CPU if none provided. It's funny that James had a great

On 02/16/2017 12:08 PM, Stephen Canon wrote: >> On Feb 16, 2017, at 9:12 AM, Bagel <bagel99 at gmail.com >> <mailto:bagel99 at gmail.com>> wrote: >> >> I figured that the optimization of this would bedifficult (else it would >> have already been done :-)) > > Don’t make this assumption. There’s lots of opportunities for optimization > scattered

On Sun, Jul 22, 2012 at 11:12 PM, Renato Golin <rengolin at systemcall.org> wrote: > On 22 July 2012 22:03, salvatore benedetto > <salvatore.benedetto at gmail.com> wrote: >> While we are at it, if a new comer would like to understand where everything >> takes place, where should he look? >> >> I did a grep in the source and eventually ended up in

> On Feb 21, 2017, at 9:54 PM, Nemanja Ivanovic via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I believe that providing additional intrinsics that would directly produce the ISD::ADDC/ISD::SUBC nodes would provide the additional advantage of being able to directly produce these nodes for code that doesn't have anything to do with multiprecision addition/subtraction. I am

On Wed, Jul 18, 2012 at 6:08 PM, salvatore benedetto <salvatore.benedetto at gmail.com> wrote: > On Wed, Jul 18, 2012 at 5:45 PM, Renato Golin <rengolin at systemcall.org> wrote: >> On 18 July 2012 15:46, salvatore benedetto >> <salvatore.benedetto at gmail.com> wrote: >>> $ clang++ -ccc-host-triple thumbv7m-none-gnueabi noInclude.cpp -c >>>

On 12 October 2013 23:00, Amara Emerson <amara.emerson at gmail.com> wrote: > Hi Jan, > > For Cortex-M0, you should probably use the armv6m string in the target > triple. For M3 and M4 you need to use the thumbv7m arch string, -mthumb > won't be necessary. > Yes, but I agree with Jim that a bug must be filled. Jan, would you mind filling a bug?

On 22 July 2012 22:03, salvatore benedetto <salvatore.benedetto at gmail.com> wrote: > While we are at it, if a new comer would like to understand where everything > takes place, where should he look? > > I did a grep in the source and eventually ended up in clang/something/driver. That's pretty much it: clang/lib/Driver

On 18 July 2012 14:33, salvatore benedetto <salvatore.benedetto at gmail.com> wrote: > but I still haven't figure out how to build for cortex-m3 > > clang -march=armv7-m -mfloat-abi=soft <something missing?> testReference.cpp -c -march should have done the trick. You can also try -mcpu=cortex-m3, or try -ccc-host-triple armv7m-none-gnueabi (or -eabi), and possibly

On 09/11/2014 05:33 PM, Quentin Colombet wrote: > Hi Brian, > > On Sep 11, 2014, at 3:03 PM, Bagel <bagel99 at gmail.com> wrote: > >> When the IR specifies a 32 bit load can it be changed to a narrower >> load? What if the load is from memory (e.g. a peripheral) that only >> supports 32-bit access? Consider the following IR: ---- target datalayout >> =