similar to: [LLVMdev] 65bit integer math

On Mon, Oct 12, 2009 at 6:15 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I have a test case(attached as fc_long.ll) that when run through the > optimizer produces 65bit integer math(fc_long-opt.ll). > > > > Now I understand that llvm can have any length integer, but I consider > turning a 64bit mul into multiple 65 bit instructions to be a ‘bad’ >

On Mon, Oct 12, 2009 at 8:22 PM, Eli Friedman <eli.friedman at gmail.com> wrote: > On Mon, Oct 12, 2009 at 6:15 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: >> I have a test case(attached as fc_long.ll) that when run through the >> optimizer produces 65bit integer math(fc_long-opt.ll). >> >> >> >> Now I understand that llvm can have any

What does nsw nuw do? Micah -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Dan Gohman Sent: Tuesday, October 13, 2009 10:06 AM To: Jeffrey Yasskin Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] 65bit integer math On Oct 12, 2009, at 9:42 PM, Jeffrey Yasskin wrote: > On Mon, Oct 12, 2009 at 8:22 PM, Eli Friedman

On Oct 12, 2009, at 9:42 PM, Jeffrey Yasskin wrote: > On Mon, Oct 12, 2009 at 8:22 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: >> On Mon, Oct 12, 2009 at 6:15 PM, Villmow, Micah <Micah.Villmow at amd.com >> > wrote: >>> I have a test case(attached as fc_long.ll) that when run through the >>> optimizer produces 65bit integer

On Monday 12 October 2009 22:22, Eli Friedman wrote: > > Now I understand that llvm can have any length integer, but I consider > > turning a 64bit mul into multiple 65 bit instructions to be a ‘bad’ > > optimization. This eventually expands to a 128bit multiply call(__multi3) > > which I have absolutely no interest in supporting. So I’m wondering what > >

On Thu, Dec 4, 2008 at 7:08 PM, Chris Lattner <clattner at apple.com> wrote: > > On Dec 4, 2008, at 8:58 AM, Villmow, Micah wrote: > > What optimization pass promotes 32 bit math operations to 64 bit operations > so I can disable it? I have code that works fine with optimizations turned > off but fails with it turned on because of this stage. > > > Do you have a

instcombine doesn't seem to be doing it. From my testing it seems to only occur when I use -indvars after a long string of commands. For example: llvm-as < test_fc_27.ll | opt -preverify -domtree -verify -lowersetjmp -raiseallocs -simplifycfg -domtree -domfrontier -mem2reg -globalopt -globaldce -ipconstprop -deadargelim -instcombine -simplifycfg -ba siccg -prune-eh -inline

-----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Eli Friedman Sent: Wednesday, September 10, 2008 3:30 PM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Custom Lowering and fneg On Wed, Sep 10, 2008 at 2:35 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Generating the following LLVM IR: > > define

Is there a simple way to specify the relationship between two different register classes of various sizes and alignments as being legal to convert between them? I have my backend written up using a single register class for i32, i64, f32 and f64 types, however, because the type information is not propagated down to the machine instruction register level, it is not known to me how to determine

What optimization pass promotes 32 bit math operations to 64 bit operations so I can disable it? I have code that works fine with optimizations turned off but fails with it turned on because of this stage. Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596

On Oct 22, 2008, at 1:28 PM, Villmow, Micah wrote: Is there a simple way to specify the relationship between two different register classes of various sizes and alignments as being legal to convert between them? I don't get it. What does it mean to "convert" between two register classes? You can move between different register classes. I am somehow hitting patterns where a

Is there a way to determine via API calls whether a pointer to an int points to a signed integer or an unsigned integer? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100512/4acff2f1/attachment.html>

On Oct 22, 2008, at 1:28 PM, Villmow, Micah wrote: > Is there a simple way to specify the relationship between two > different register classes of various sizes and alignments as being > legal to convert between them? I don't get it. What does it mean to "convert" between two register classes? You can move between different register classes. > I have my backend

On Dec 4, 2008, at 8:58 AM, Villmow, Micah wrote: > What optimization pass promotes 32 bit math operations to 64 bit > operations so I can disable it? I have code that works fine with > optimizations turned off but fails with it turned on because of this > stage. > Do you have a testcase? An .ll file with no 64-bit operations, and one optimization pass that introduces

So, I have this small test program that I figured would cause no problems but want to test all the various data types and operations with my modified sparc backend. I've been working on LLVM for about 3 days now, so this might be a problem with not knowing enough yet, so thanks for bearing with me. The code that I based my example off of is compiled to LLVM-IR from: void

From: metafoo at gmail.com [mailto:metafoo at gmail.com] On Behalf Of Richard Smith Sent: Wednesday, September 12, 2012 3:30 PM To: Villmow, Micah Cc: Eli Friedman; cfe-dev at cs.uiuc.edu; llvmdev at cs.uiuc.edu Subject: Re: [cfe-dev] [LLVMdev] SPIR Portability Discussion On Wed, Sep 12, 2012 at 3:26 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote:

On 13 May 2010 05:28, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Is there a way to determine via API calls whether a pointer to an int points > to a signed integer or an unsigned integer? > Since LLVM doesn't have signed or unsigned integer types, I'm not sure what you're asking. I suppose you could look for additions done with values loaded from or stored to

> -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Wednesday, September 12, 2012 3:50 PM > To: Villmow, Micah > Cc: Richard Smith; cfe-dev at cs.uiuc.edu; llvmdev at cs.uiuc.edu > Subject: Re: [cfe-dev] [LLVMdev] SPIR Portability Discussion > > On Wed, Sep 12, 2012 at 3:40 PM, Villmow, Micah <Micah.Villmow at amd.com> >

> -----Original Message----- > From: Eli Friedman [mailto:eli.friedman at gmail.com] > Sent: Thursday, August 30, 2012 3:03 PM > To: Villmow, Micah > Cc: LLVM Developers Mail > Subject: Re: [LLVMdev] FW: RFC: Supporting different sized address space > arithmetic > > On Thu, Aug 30, 2012 at 2:38 PM, Villmow, Micah <Micah.Villmow at amd.com> > wrote: > >

Ahh yep, thanks for catching that, new patch attached. > -----Original Message----- > From: Hal Finkel [mailto:hfinkel at anl.gov] > Sent: Tuesday, July 31, 2012 1:40 PM > To: Villmow, Micah > Cc: Developers Mailing List > Subject: Re: [LLVMdev] Vector promotion broken for <2 x [i8|i16]> > > Micah, > > I think that your patch is missing the necessary