similar to: [LLVMdev] Re presenting SIMT programs in LLVM

Hello All, I build source code of Ocelot[http://code.google.com/p/gpuocelot/]. It using LLVM dependency of Ocelot. llvm-config get cppflags represent as below in order to build with Ocelot. ./llvm-config --cppflags -I/home/chatsiri/workspacecpp/llvm/include -I/home/chatsiri/workspacecpp/llvm/include -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS

Hi Marcello, On Fri, Oct 19, 2012 at 04:38:29PM +0100, Marcello Maggioni wrote: > Hello, > I'm working on a compiler based on LLVM for a SIMD architecture that > supports instruction predication. We would like to implement branching > on this architecture using predication. > As you know the LLVM-IR doesn't support instruction predication, so I'm > not exactly

On Tue, Dec 13, 2011 at 3:37 PM, Villmow, Micah <Micah.Villmow at amd.com>wrote: > ** ** > > *From:* Justin Holewinski [mailto:justin.holewinski at gmail.com] > *Sent:* Tuesday, December 13, 2011 10:50 AM > > *To:* Villmow, Micah > *Cc:* LLVM Developers Mailing List > *Subject:* Re: [LLVMdev] Changes to the PTX calling conventions**** > > ** ** > > On

From: Justin Holewinski [mailto:justin.holewinski at gmail.com] Sent: Tuesday, December 13, 2011 10:50 AM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Changes to the PTX calling conventions On Tue, Dec 13, 2011 at 12:54 PM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote: From: Justin Holewinski [mailto:justin.holewinski

2011/12/14 Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi> > Hi all, > > On 12/13/2011 10:50 PM, Justin Holewinski wrote: > > You mean having no calling convention for device functions, and a new, > common > > calling convention for kernels? > > I think this might make sense. > To be clear, I do like the idea of using the default calling convention for

Hi I am interested to know: are there are any LLVM targets in the works for Nvidia's PTX ISA? Also if anyone knows about Ocelot (a project done by some students at my school): it does the opposite of what I am trying to do (translates PTX to LLVM IR to run Cuda kernels on the CPU). Thanks in advance. -Puyan

Hi, there I am quite sure there is an easy answer to this, but I am unsure how to gather a bunch of t-statistics in an organized format. I am trying to generate a list of t-statistics for a randomization routine. If I try to collect a bunch of t-statistics from a run, this is what happens: > M <- 10 ; simt <- NULL > for(i in 1:M) + { + perm<-sample(site,replace=F) + +

On Mar 26, 2010, at 11:28 PM, Puyan Lotfi wrote: > Hi > > I am interested to know: are there are any LLVM targets in the works > for Nvidia's PTX ISA? > > Also if anyone knows about Ocelot (a project done by some students at > my school): it does the opposite of what I am trying to do (translates > PTX to LLVM IR to run Cuda kernels on the CPU). I don't know of

(I work on CUDA / PTX.) For one thing I'm in favor of having fewer annotations rather than more, so if we can do this in a reasonable way without introducing the notion of co-convergent calls, I think that would be a win. The one convergent annotation is difficult enough for the GPU folks to grok and then keep in cache, and everyone who works on llvm has to pay the cost of keeping their

Hi, (Disabling lurk mode) I must admit, I believe this would be an extremely valuable addition to llvm, to the point where I was also seriously considering writing this backend. The main thing holding me back is the thought that other people are almost certainly working on the same thing (probably including nvidia)! I assume it's not yet ready to publish, but it's worth

On Tue, Dec 13, 2011 at 12:54 PM, Villmow, Micah <Micah.Villmow at amd.com>wrote: > ** ** > > ** ** > > *From:* Justin Holewinski [mailto:justin.holewinski at gmail.com] > *Sent:* Tuesday, December 13, 2011 9:48 AM > *To:* Villmow, Micah > *Cc:* LLVM Developers Mailing List > *Subject:* Re: [LLVMdev] Changes to the PTX calling conventions**** > > ** ** >

From: Justin Holewinski [mailto:justin.holewinski at gmail.com] Sent: Tuesday, December 13, 2011 9:48 AM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Changes to the PTX calling conventions On Tue, Dec 13, 2011 at 11:25 AM, Villmow, Micah <Micah.Villmow at amd.com<mailto:Micah.Villmow at amd.com>> wrote: Currently, PTX has its own calling conventions where

I'm going to setup rsync for web pages synchronziation between two linux servers. how do I change files, folders owner of dest ? for example the files owner of remote host is uid mary, after executed rsync for file synchronization, the files owner of local host will be uid peter, instead of mary which option or paramter to do this ?

Why is this a regalloc problem? I assume in the example below the "r0" is somehow forced by the ABI? Because otherwise moving the texture2d operation into the branch wouldn't matter as long as we assign different registers to the two branches and use a technique like lib/Target/R600/SIFixSGPRLiveRanges.cpp. - Matthias > On May 13, 2015, at 6:00 PM, Philip Reames <listmail at

Hi Jingyue, Convergent is not intended to prevent inlining. It’s tricky to formalize this inter-procedurally, but the intended interpretation is that a convergent operation cannot be move either into or out of a conditionally executed region. Normal inlining would not violate that. I would imagine that it would make sense to use a combination of convergent and noduplicate for barrier-like

Hi Mehdi, My reading of it is that if you have a convergent instruction A, it is legal to duplicate it to instruction B if (assuming B is after A in program flow) A dominates B and B post-dominates A. James On Fri, 14 Aug 2015 at 08:32 Mehdi Amini via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On Aug 13, 2015, at 9:43 PM, Owen Anderson via llvm-dev < > llvm-dev at

Hi Owen and Vinod, Thanks for sharing the paper! I like the idea a lot. Regarding the paper itself, Vinod, are the consensual branches (e.g., cbranch.ifnone) you mentioned in the paper publicly available in PTX ISA? Owen, could you explain more on the approach of using branch-if-none instructions in your mind? I believe you have lots of great insights, but I don't see how cbranch.ifnone

On 12/14/2011 02:41 PM, Justin Holewinski wrote: > I would favor calling conventions over metadata for the simple reason > that this maps more cleanly to the device model. Device and kernel > functions are represented differently in PTX, including (sometimes) the > way parameters are passed. For the record, marking the kernels with "calling conventions" instead of metadata

2011/12/14 Pekka Jääskeläinen <pekka.jaaskelainen at tut.fi> > On 12/14/2011 02:41 PM, Justin Holewinski wrote: > >> I would favor calling conventions over metadata for the simple reason >> that this maps more cleanly to the device model. Device and kernel >> functions are represented differently in PTX, including (sometimes) the >> way parameters are passed.

Adjust drivers that support the 'FLOW_DISSECTOR_KEY_META' key to reject filters that try to match on the newly added layer 2 miss option. Add an extack message to clearly communicate the failure reason to user space. Example: # tc filter add dev swp1 egress pref 1 proto all flower skip_sw l2_miss true action drop Error: mlxsw_spectrum: Can't match on "l2_miss". We have