similar to: [LLVMdev] Help with gcc SSE intrinsics

On Oct 9, 2009, at 1:26 PMPDT, David Greene wrote: > Ok, I've been looking at this for hours and can't figure it out. I > know I'm > missing something obvious. > > I've been spending the past few days beefing up the vector support > in the C > Backend. This should help us debug vector code that's miscompiled. > But > gcc doesn't like

On Friday 09 October 2009 15:47, Dale Johannesen wrote: > On Oct 9, 2009, at 1:26 PMPDT, David Greene wrote: > > Ok, I've been looking at this for hours and can't figure it out. I > > know I'm > > missing something obvious. > > > > I've been spending the past few days beefing up the vector support > > in the C > > Backend. This should

Hi Devs, Consider below testcase. $cat test.cpp #include <vector> #include<type_traits> typedef int _int4 __attribute__((vector_size(16))); typedef union{ int data[4]; struct {int x, y, z, w;}; _int4 vec; } int4; typedef int4 int3; int main() { static_assert(std::alignment_of<int4>::value <= alignof(max_align_t), "over aligned!"); } $clang++ -m32 error:

The following code is causing me problems in the Sparc back-end and I believe it's related to a lot of issues that I have, so I'd love to work out what I need to do to resolve this. I'm currently not making much headway into it. I'm going to try to simplify this to the core problem I can see and hope I haven't missed anything relevant. The original code I have is as follows:

Hi All, If the target supports quad-register R0:R1:R2:R3 (Rn is 32-bit register), is it possible mapping quad-register to v4i32 so that the following example work? typedef int v4si __attribute__ ((vector_size (16))); void foo(v4si i) { v4si j = i; } I don't know how to write CallingConv.td to represent the concept of occupying quad-register R0:R1:R2:R3 once seeing

Hi Krzysztof, Thanks for response. The method is working almost of test cases which use load and store instructions connected with chain. There is other situation. Let's look at a example as follows: typedef unsigned short int UV __attribute__((vector_size (8))); void test (UV *x, UV *y) { *x = *y / ((UV) { 4, 4, 4, 4 }); } The target does not support vector type so CodeGen tries to

Hi Bruce, Thanks for response. I also think it is not good way. Do you have the other ways to legalize it? Thanks, JinGu Kang 2016-02-01 13:11 GMT+00:00 Bruce Hoult <bruce at hoult.org>: > In fact this is a pretty bad legalizing/lowering because you only need to > load and edit for the first and last values in the vector. The other words > are completely replaced and don't

Hi Anton, I assume that's the same as the online demo's "Show LLVM C++ API code" option (http://llvm.org/demo/)? I've tried that with a structure containing four floating-point components but it also appears to add them individually using extract/insert. Maybe I have to try an array of floats... Thanks, Anton -----Original Message----- From: llvmdev-bounces at

Nicolas, > Thanks for the advise, but I'm actually not trying to compile code from > text. For now I'm just trying to construct the function directly. Think of > it as the vector equivalent of the HowToUseJIT.cpp example. llvm2cpp is your friend then. It's now a separate 'target' in llc. It will generate C++ code, which will construct provided IR. -- With best

> I may be missing something obvious, but what is `vector` defined as here? Can you provide a buildable example? Sorry, I should provide a cross-platform version using vector extension of frontend :) `vector int` is a vector extension on PowerPC, which is enabled if you set target to PowerPC platforms. Example below should be successfully compiled in any platform: typedef float v4sf

While solving a clang build issue with netpbm10 on fink darwin11, I noticed that clang seems to provide poor error messages compared to llvm-gcc. For llvm-gcc, we get the very helpful warning... libpbm3.c: In function 'packBitsWithMmxSse': libpbm3.c:120: warning: specifying vector types with __attribute__ ((mode)) is deprecated libpbm3.c:120: warning: use __attribute__ ((vector_size))

Bob Wilson writes: > On Sep 21, 2010, at 9:33 AM, Renato Golin wrote: > > I was checking NEON instructions this week and the vector types seem > > to be inside structures. If vector types are considered proper types > > in LLVM, why pack them inside structures? > > Because that is what ARM has specified? They define the vector types > that are used with their NEON

Hi all, I have a backend for an in house architecture, and would like to start working on support for vector datatypes and intrinsics. As I starter I would like to have vector code scalarized, as is done, e.g., for the Mips backend. However, I cannot find a way to force the instruction selector or type legalizer to scalarize the vectors (i.e., vector types and vector ops). Can anyone help me out?

> On Dec 5, 2018, at 8:46 PM, John McCall <jmccall at apple.com> wrote: > > On 5 Dec 2018, at 13:41, Adam Nemet wrote: >> ------------------------- >> Proper padding for small matrices >> ------------------------- >> >> We want the individual rows/columns (for row/column-major) to be naturally aligned by no more than the max vector alignment. E.g.

The following code causes opt to not terminate! With TOT this morning, and of a week ago: clang foo.c and clang -O1 foo.c work fine. clang -O2 foo.c and clang -O3 foo.c do not terminate. (At least after 10 minutes) If I generate the bit code (clang-cc -emit-llvmbc) and then run: opt -O3 foo.bc it does not terminate. //foo.c int get_id(int); typedef short

I finally got all of the 3DNow! instruction intrinsics and builtins into LLVM and Clang, however, while testing them, I've noticed that they produce incorrect results. For example: typedef float V2f __attribute__((vector_size(8))); int main() { V2f dest, a = {1.0, 3.0}, b = {10.0, 3.5}; dest = __builtin_ia32_pfadd(a, b); printf("(%f, %f)\n", dest[0], dest[1]); } Should

Canonicalizing to a masked store intrinsic is possible, but we might have to expand back to the load/shuffle/store sequence for targets that don't support masked store. And then you'd likely have to do the store splitting that I think is being requested for the original pattern anyway. But I'd like to step back to the premise - "LLVM seems to always generate vector instructions

I wrote the following program: #include <stdio.h> int main() { float a=1, b=2, c=3, d=4; float e=1, f=2, g=3, h=4; for (int i=0; i<1000000000; ++i) { a += e; b += f; c += g; d += h; e /= a; f /= b; g /= c; h /= d; } printf("%f %f %f %f\n", a, b, c, d); return 0; } and compiled it with: llvm-gcc -std=c99 -O3 -msse3 vector.c -o

Hi all, I have the following problem: I want to call a function from llvm (tryf in the following) which takes a vector as an argument. The function tryf is a c-function and should output the whole vector. But I only get 0.0. Looks like a problem with how the arguments are passed. I havn't found anything in the docs about how vectors are passed. Any help would be appreciated. The llvm-code

I'm not clear, but it sounds like maybe your issue is not just alignment, but that you have no 1/2-byte load or store operations at all on your target? Do you mean that to do any 2-byte store, even if it's naturally aligned, you need to load the 4-byte word that contains it, replace the low or high half as appropriate, and then use a 4-byte store to store back the modified value? On Fri,