similar to: [LLVMdev] TableGen question - how to split a 64bit operation to two 32bit

Hi Artur, The Thumb2 target (in lib/Targets/ARM/ARMInstrThumb2.td) materializes a 32-bit constant by a two-instruction sequence to load the low and high half-words. It's not pretty, but it works. The pattern is at the bottom of the file. Regards, -Jim On Oct 6, 2009, at 5:10 AM, Artur Pietrek wrote: > Hi all, > I'm working on my own backend for a custom CPU. I have defined

Hello, I work in Kalray (Montbonnot, France) and I'm PhD student at Universite Joseph Fourier in Grenoble. We want to use LLVM framework for MSIL code generation, which is part of my thesis. Currently I'm still reading LLVM's documentation and I've started completing the MSIL backend for running on Mono. Things that need to be fixed include pointers initialization, call to

Hi Jean-Daniel On Mon, Oct 19, 2009 at 3:24 PM, Jean-Daniel Dupas <devlists at shadowlab.org>wrote: > > Le 19 oct. 2009 à 15:05, Kenneth Uildriks a écrit : > FWIW, there is a LLVM bar camp planed in Paris the next month: > > http://barcamp.org/LLVM%20BarCamp%20Paris (French web page) > > > -- Jean-Daniel > Could you please tell me if it will be in French or

I updated DwarfDebug to use section offset, instead of hard coding 0, to handle LTO properly. r107202. Thanks for brining this up. - Devang On Tue, Jun 29, 2010 at 11:27 AM, Devang Patel <devang.patel at gmail.com> wrote: > DW_AT_stmt_list attribute's value is a section offset to the line no > info for current compilation unit. If there is only one  compilation > unit

On Thu, Apr 15, 2010 at 3:40 AM, Artur Pietrek <pietreka at gmail.com> wrote: > Hi all > Ups, I'm really sorry for that previous message, I've sent it by mistake. > > So let me write it once more. > > I've been working for some time now on a backend for our CPU. However I > couldn't figure out how to implement some stuff. > I'd appreciate your help

Hi All, Since few days I observe weird change. Consider the following C code char array[] = "0123456789"; extern int test(char arr[], int size); int main(void) { return test(array-1, sizeof(array)-1); } using clang frontend i get this: %call = call i32 @test(i8* getelementptr inbounds ([11 x i8]* @array, i32 0, i32 -1), i32 10) ; <i32> [#uses=1] and using LLVM-GCC this: %1 =

Hi all, While implementing debug info for our backend, we've noticed a problem with debug_line section. We believe that the following code is wrong: // DW_AT_stmt_list is a offset of line number information for this // compile unit in debug_line section. It is always zero when only one // compile unit is emitted in one object file. addUInt(Die, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4,

On Aug 31, 2010, at 2:15 AM, Renato Golin wrote: > On 26 August 2010 09:32, Krister Wombell <kuwerty at gmail.com> wrote: >> I've also been looking at debugging with ELF and noticed the same problem as >> Renato. I just sent a patch to llvmcommits that fixes the problem. >> DW_at_stmt_list needs to emit a label(and therefore a relocation) for the >> offset

On Fri, Aug 21, 2009 at 12:33 PM, Eli Friedman <eli.friedman at gmail.com>wrote: > On Fri, Aug 21, 2009 at 2:02 AM, Artur Pietrek<pietreka at gmail.com> wrote: > > Hi All, > > Since few days I observe weird change. > > Consider the following C code > > > > char array[] = "0123456789"; > > extern int test(char arr[], int size); > >

Here basically my problem is vector width since i have used v64i32 in my backend. now if vector width=64. i want the Reg_B class registers to be assigned and if vector width=2048 i want Reg_A registers to be assigned to instruction. Should i incorporate the solution in lowering stage? some thing like; addRegisterClass(MVT::v2048i32, &X86::Reg_B);

Hi Anton, Thanks for reply > I have defined registers, aliases and subregister set. > > The problem is that register allocator is using 32bit registers that are > > already used in a pair, for example: > > lw $r0, 16[$r12] // load word to r0 > > ld $p0, 36[$r12] // load doubleword to p0 > > shl $p0, $p0, $r0 // shift left p0 by r0 and store result in p0

Hi Artur, Artur Pietrek wrote: > Hello, > > I work in Kalray (Montbonnot, France) and I'm PhD student at Universite > Joseph Fourier in Grenoble. > We want to use LLVM framework for MSIL code generation, which is part of > my thesis. > Currently I'm still reading LLVM's documentation and I've started > completing the MSIL backend for running on Mono.

Le 20 oct. 2009 à 10:27, Artur Pietrek a écrit : > Hi Jean-Daniel > > On Mon, Oct 19, 2009 at 3:24 PM, Jean-Daniel Dupas <devlists at shadowlab.org > > wrote: > > Le 19 oct. 2009 à 15:05, Kenneth Uildriks a écrit : > FWIW, there is a LLVM bar camp planed in Paris the next month: > > http://barcamp.org/LLVM%20BarCamp%20Paris (French web page) > > > --

hello, i have a situation where i have to assign the registers to instructions based on the loop iterations. for eg.. the registers are: R_0_V_0, R_0_V_1, R_0_V_2, R_0_V_3, R_1_V_0, R_1_V_1, R_1_V_2, R_1_V_3, R_2_V_0, R_2_V_1, R_2_V_2, R_2_V_3. These registers defined in object Reg_A These are total 12 registers. will use them contiguously, here i define it in above mentioned order i.e

Hi Andrew, thanks for answering On Thu, Apr 15, 2010 at 3:35 PM, Andrew Lenharth <andrewl at lenharth.org>wrote: > On Thu, Apr 15, 2010 at 3:40 AM, Artur Pietrek <pietreka at gmail.com> wrote: > > Hi all > > Ups, I'm really sorry for that previous message, I've sent it by mistake. > > > > So let me write it once more. > > > > I've

DW_AT_stmt_list attribute's value is a section offset to the line no info for current compilation unit. If there is only one compilation unit generated per .o file then it is always zero. What kind of errors are you seeing ? - Devang On Tue, Jun 29, 2010 at 9:02 AM, Artur Pietrek <pietreka at gmail.com> wrote: > Hi all, > While implementing debug info for our backend, we've

Hi Devang, Thanks for working on that. Unfortunately after your change it still doesn't work (I've tried x86 and our backend under Linux). The problem is that you put difference between two labels .Lset7 = .Lsection_line_begin-.Lsection_line ## DW_AT_stmt_list and that will be evaluated by assembler to a constant. It has to be a label, not a constant, because it is the linker who knows

Hi all, I've been working for some time now on a backend for our CPU. However I couldn't figure out how to implement some stuff. I'd appreciate your help with these. First thing is return address -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100415/989f532c/attachment.html>

Hi all, while I was playing a little bit with IRBuilder I ended up with something like this when included NoFolder.h /work/llvm/include/llvm/User.h: In member function ‘llvm::Value* llvm::NoFolder::CreateExtractElement(llvm::Constant*, llvm::Constant*) const’: /work/llvm/include/llvm/User.h:48: error: ‘static void* llvm::User::operator new(size_t)’ is private

Hi all Ups, I'm really sorry for that previous message, I've sent it by mistake. So let me write it once more. I've been working for some time now on a backend for our CPU. However I couldn't figure out how to implement some stuff. I'd appreciate your help with these. First thing is return address saving. To do that, first I have to copy it to a general purpose register. I