similar to: [LLVMdev] About porting llvm-gcc frontend.

Hi 任坤, > void vfu1(union MYunion u) { > u.ui = 99; > } here u is passed by copy, so vfu1 has no externally visible effect. I think you meant: union MYunion *u > define void @vfu1(%struct.MYunion* byval align 4 %u) nounwind { Here "byval" means that a pointer to a temporary copy of u is being passed, not u itself. Thus any writes to the %u parameter have no effect

Hi, EveryOne: I am travelling CFG with MachineFunction. So I want to sure it. (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really? best regards. ___________________________________________________________ 好玩贺卡等你发，邮箱贺卡全新上线！ http://card.mail.cn.yahoo.com/ -------------- next part -------------- An HTML attachment was scrubbed...

Dear Evan Chang: I register incorrect Register class for MVT::f64. I have fixed it. Thanks your advice. "-view-legalize-dags" is very good option. But I don't know why my LLC do not know " -view-legalize-type-dags" option. By the way, I use llvm 2.5 merged from llvm2.4. Best Regards, Ren Kun --- 09年3月31日，周二, Evan Cheng <echeng at apple.com> 写道： 发件人: Evan Cheng

hi, Dear Evan Cheng: My cpu is i32 embeded CPU. I define pseudo register pair registers. In mytargetRegisterInfo.td: def T0: RegisterWithSubRegs<"t0",[R0,R1]>; ... def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] In mytargetISelLowering.cpp: I define i1, i8 , i16 and i32 are legal. 1. I still have problem. I save my function return double  value in

Fairly straightforward code motion of MSR / TSC / PMC accessors to the sub-arch level. Note that rdmsr/wrmsr_safe functions are not moved; Linux relies on the fault behavior here in the event that certain MSRs are not supported on hardware, and combining this with a VMI wrapper is overly complicated. The instructions are virtualizable with trap and emulate, not on critical code paths, and only

Fairly straightforward code motion of MSR / TSC / PMC accessors to the sub-arch level. Note that rdmsr/wrmsr_safe functions are not moved; Linux relies on the fault behavior here in the event that certain MSRs are not supported on hardware, and combining this with a VMI wrapper is overly complicated. The instructions are virtualizable with trap and emulate, not on critical code paths, and only

Hi: I hope to cut all backedges of MachineFunction CFG, then topological sort MachineBasicBlocks. 1. MachineDominatorTree *domintree = new MachineDominatorTree(); domintree->runOnMachineFunction(mf); 2. Then travel mf one by one. When domintree->dominates(next,current) is true, there is a backedge from current node to next node. move this backedge form CFG. But I find A LOOP in

I try to define a register class def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] to simulate even/odd pair of GPR32 register. Actually, I just use GPR64 as a temporary register. My CPU just support i32 Integer type directly. I use FDR to save f64. def FDR : RegisterClass<"mytarget", [f64], 64,[FD0, FD1, ....] When I move f64 to even/odd pair register, I

Dear R helpers Suppose val1 = c(10, 20, 35, 80, 12) val2 = c(3, 8, 11, 7) I want to select either val1 or val2 depending on value of third quantity val3. val3 assumes either of the values "Monthly" or "Yearly". If val3 = "Monthly", then val = val1 and if val3 = "Yearly", then val = val2. I tried the ifelse statement as ifelse(val3 =

On Feb 19, 2009, at 8:26 PM, 任坤 wrote: > hi, Dear Evan Cheng: > > My cpu is i32 embeded CPU. I define pseudo register pair registers. > > In mytargetRegisterInfo.td: > def T0: RegisterWithSubRegs<"t0",[R0,R1]>; > ... > def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....] > > In mytargetISelLowering.cpp: > I define i1, i8 ,

Hello, I'm trying to compile vmkit on a x86_64 linux box with gcc-4.1.2, but I'm running into troubles because of various problems with casts between pointers and integers. Is there anybody who succeeded in this task? Az I see, some of the problems can be fixed with an appropriate typedef/macro declaration, but in VMCore/JavaObject.cpp some lowlevel bitmanipulation is used, to mark

Hi Zsombor, Thanks for the patch! Unfortunately I can't apply it because the llvm API has moved from BinaryOperator::create to BinaryOperator::Create. Are you using svn head? Now on the x86_64 part. There has been very little work on porting vmkit on x86_64. If you're having compilation problems, I suppose it's in the garbage collector directory (GCMmap2). If you could make the

On Dec 3, 2009, at 9:52 PM, 任坤 wrote: > Hi, EveryOne: > > I am travelling CFG with MachineFunction. So I want to sure it. > (Preccessors' Number) < MachineBasicBlock's Number < (Successors's Number), Is it really? > Hi 任坤, I can't say for sure, though I don't think we make assurances that this is the case. If you want to traverse the CFG, there should

Hi, I have ported LLC to a risc cpu. It can pass benchmark that I have at current. But I want do some optimization after register alloction by adjusting register using. I scan MachineBasicBlock to analyze operand's IsKill, IsDead , IsDef attribute to get a physical register's liverange. But I get a strange case at MBB.jpg. R4 is marked <kill> at MBB0. If I scan R4's

What is the best way to produce a barplot from my data? I would like the barplot to show each person with the values stacked val1+val2+val3, so there is one bar for each person When I use barplot(data.matrix(realdata)), it shows one bar for each value instead. To post here, I created an artificical data set, but it works fine. fakedata <- as.data.frame(list(LETTERS[1:3])) colnames(fakedata)

When CONFIG_PARAVIRT is enabled, the kernel is ignoring exceptions on the {rd,wr}msr instructions. This makes serious issues (either on the guest kernel, or on the host) be silently ignored, and is different from the native MSR code (which does not ignore the exceptions). As paravirt.h already includes linux/bug.h, I don't see what was the original issue preventing BUG_ON from being used.

When CONFIG_PARAVIRT is enabled, the kernel is ignoring exceptions on the {rd,wr}msr instructions. This makes serious issues (either on the guest kernel, or on the host) be silently ignored, and is different from the native MSR code (which does not ignore the exceptions). As paravirt.h already includes linux/bug.h, I don't see what was the original issue preventing BUG_ON from being used.

Hi, I have data like this.... print(x) ID VAL1 VAL2 1 B A 2 P Q 3 T S What I would like is data like this... ID VAL1 VAL2 1 A B 2 P Q 3 S T So that VAL1 and VAL2 are alphabetically ordered. Any advice is welcome! San. [[alternative HTML version deleted]]

Hi, I have the following test case: define void @foo(<2 x float>* noalias nocapture %out, <2 x float>* noalias nocapture %data0) nounwind { entry: %val1 = load <2 x float>* %data0, align 8 store <2 x float> %val1, <2 x float>* %out, align 8 fence acq_rel %val2 = load <2 x float>* %data0, align 8 store <2 x float> %val2, <2 x float>*

Hi, I'm trying to plot stacked barplot with lines on it. Here is the data. emp days val1 val2 score 1 21 1 0 1200 2 35 1 1 na 3 42 na na 3000 4 53 2 1 2100 5 64 1 0 na 6 73 na na 1400 My X-axis is days. I'm looking to plot val1,val2 as stacked bars and score as lines with different y-axis. I could get the bar plot and lines on it but the problem is the bars and lines are not aligning