similar to: [LLVMdev] Basic question concerning phi nodes and SSA variable labelling.

Hi All, Another nls related problem (for background, I'm migrating a complicated modelling package from S-plus to R). Below I've reduced this to the minimum necessary to demonstrate my problem (I think); the real situation is more complicated. Two similar selfStart functions, ssA and ssB. The 'initial' function for ssB modifies its arguments a little and then calls getInital

Hi, I have been looking at the LLVM JIT system as a basis for a project I am working on and had a few beginner's questions which I was hoping someone might be able to answer and which I haven't yet been able to figure out reading the source code. If anyone could provide some help I would appreciate it. 1) How does one go about calling a precompiled function external to the JIT from a JIT

Hi, is there any standard way to figure out the label of the basic block where a conditional branch merges? If we have a branch statement without an else part this is straightforward: br i1 %cmp, label %if.then, label %if.end, !dbg !24 We only need to check the operand names whether they contain "end". However things are getting more complex when there is an else branch and in

I have been toying around with the LLVM tutorial code and I am trying to deduce what I can from it as a basis for a compiler frontend for a simple language of my own devising (once I understand what I am doing I will probably attempt mapping a more complex language target). I am having some difficulties however understanding how certain things work and I was hoping perhaps someone could help me

On Mon, Jul 20, 2009 at 4:15 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > This is probably another very basic question- but is there a simple method for cross compiling LLVM for another platform? If you already have a cross-compiling environment set up, it shouldn't be too hard; for LLVM and llvm-gcc, you should be able to pass in --host=mytarget to configure, and if

On Mon, Jul 27, 2009 at 8:56 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > Is there also an option to compile w/ clang on an x86 for Mipsel? A normal build of clang includes limited cross-compile support by passing in the "-ccc-host-triple" option, although it's still a bit of a work-in-progress. Nobody has added support for any Mips targets, but it's really

Yes. But it is not really being used by most (any?) targets because post-RA scheduling is disabled by default. Also, the existing model is very limited in what types of micro-architectures can be described. I've been extending it to enable scheduling of multi-issue targets, targets with overlapping FU usage, and targets that use and define registers in multiple pipeline stages. See

On Sun, Jun 28, 2009 at 1:05 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > 1) Using the Builder interface how does one create the equivalent of stack frames and access variables in the current stack frame or perhaps in the static enclosing scope (assuming functions can be nested)? To create stack variables, you can use the alloca instruction; see

Hi, I know this is probably a basic question... But I don't seem to find the answer. I'm fitting a GLM with a Poisson family, and then tried to get a look at the predictions, however the offset does seem to be taken into consideration: model_glm=glm(cases~rhs(data$year,2003)+lhs(data$year,2003), offset=(log(population)), data=data, subset=28:36, family=poisson()) predict

Actually after some digging I managed to answer these questions for myself. I am guessing that this information is used by the Schedule* classes in CodeGen. --- On Mon, 8/17/09, Carter Cheng <carter_cheng at yahoo.com> wrote: > From: Carter Cheng <carter_cheng at yahoo.com> > Subject: [LLVMdev] ARMSchedule.td MipsSchedule.td etc. > To: llvmdev at cs.uiuc.edu > Date:

On Jun 25, 2009, at 4:38 PM, David Goodwin wrote: > Using the Thumb-2 target we see that ORN ( a | ^b) and BIC (a & ^b) > have similar patterns, as we would expect: > > defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node: > $RHS))>>; > defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node: >

On Jun 25, 2009, at 6:06 PM, Evan Cheng wrote: > > On Jun 25, 2009, at 4:38 PM, David Goodwin wrote: > >> Using the Thumb-2 target we see that ORN ( a | ^b) and BIC (a & ^b) >> have similar patterns, as we would expect: >> >> defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not >> node:$RHS))>>; >> defm t2ORN :

I am curious- what is the current status of the MIPS support in LLVM? I have a mipsel device and was wondering if I could compile code for it with clang. Would I have to implement a backend setup myself? Is there also an option to compile w/ clang on an x86 for Mipsel? Thanks in advance.

Hi, I have been trying to move some instructions between basic blocks , After looking at the API , I found llvm::Instruction::clone() but there is no result value for this. For example- source Basic block : continuation: ; preds = %else, %then %iftmp = phi i32 [ 5, %then ], [ 9, %else ] store i32 %iftmp, i32* %datasize ; 3 instructions below

Thanks Duncan, I know about list2env(), in fact a previous version of collapse::`%=%` was coded as "%=%" <- function(lhs, rhs) { if(!is.character(lhs)) stop("lhs needs to be character") if(!is.list(rhs)) rhs <- as.vector(rhs, "list") if(length(lhs) != length(rhs)) stop("length(lhs) not equal to length(rhs)") list2env(`names<-`(rhs,

I apologize if this has been asked before but which classes utilize the information in these files? I am asking since I am trying to extend the MIPS backend to 64bit among other things. Thanks in advance, Carter.

Hi, I am emitting llvm bit code using llvm-gcc -c -emit-llvm -O0 -o test.bc test.c and then optimizing it with opt -O3 -print-module test.bc in order to obtain a dump of generated IR. The resulting code has Phi nodes and is perhaps in SSA form. I want to undo the SSA form while retaining all the other optimizations. Is mem2reg the right optimization to be added after -O3, i.e., opt -O3

Using the Thumb-2 target we see that ORN ( a | ^b) and BIC (a & ^b) have similar patterns, as we would expect: defm t2BIC : T2I_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node: $RHS))>>; defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node: $RHS))>>; Compiling the following three works as expected: %tmp1 = xor i32

On 01/22/2011 10:30 PM, Surinder wrote: > Hi, > > I am emitting llvm bit code using > > llvm-gcc -c -emit-llvm -O0 -o test.bc test.c > > and then optimizing it with > > opt -O3 -print-module test.bc > > in order to obtain a dump of generated IR. > > > The resulting code has Phi nodes and is perhaps in SSA form. I want > to undo the SSA form while

Hi Evan, > LValue LV = EmitLV(lhs); > bool isVolatile = TREE_THIS_VOLATILE(lhs); > unsigned Alignment = expr_align(exp) / 8 > > It's using the alignment of the expression, rather than the memory > object of LValue. can't you just use expr_align(lhs) instead? > The patch saves the alignment of the memory object in LValue returned > by EmitLV().