similar to: [LLVMdev] Target Intrinsics via Tablegen

> -----Original Message----- > From: Jim Grosbach [mailto:grosbach at apple.com] > Sent: Monday, November 08, 2010 10:41 AM > To: Villmow, Micah > Cc: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Creating tablegen patterns for intrinsics with > no return value. > > > On Nov 8, 2010, at 10:32 AM, Villmow, Micah wrote: > > > I have intrinsic with no

On Nov 8, 2010, at 10:32 AM, Villmow, Micah wrote: > I have intrinsic with no return value and I need to match them to machine instructions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted. Hi Micah, >From your description it sounds like machine dead code elimination is

On Wed, Apr 15, 2009 at 11:15 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I still think there is a bug somewhere, but not sure where yet. > This is what is generated in intrinsic.gen: > case Intrinsic::opencl_math_fdistance:          // > llvm.opencl.math.fdistance >    ResultTy = Type::FloatTy; >    ArgTys.push_back(Tys[0]); >    ArgTys.push_back(Tys[0]);

Are you using isTarget = 1 in your intrinsics file? On Apr 14, 2009, at 6:34 PM, Villmow, Micah wrote: > It seems that Tablegen is generating intrinsic ID’s off by in > DAGISel.inc > > In DAGISel.inc, I have the following pattern: > int64_t CN1 = Tmp0->getZExtValue(); > > // Pattern: (intrinsic_w_chain:f32 103:iPTR, GPRF32:f32:$src0, > GPRF32:f32:$src1,

I still think there is a bug somewhere, but not sure where yet. This is what is generated in intrinsic.gen: case Intrinsic::opencl_math_fdistance: // llvm.opencl.math.fdistance ResultTy = Type::FloatTy; ArgTys.push_back(Tys[0]); ArgTys.push_back(Tys[0]); break; This is the intrinsic definition: def int_opencl_math_fdistance_fast : Intrinsic<[llvm_float_ty],

I have intrinsic with no return value and I need to match them to machine instructions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted. Here is my profile/node/pattern. Profile: def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [ SDTCisPtrTy<0>, SDTCisVT<1, i32>,

I believe multiclasses can be nested. Could that help you reduce the duplication? --Sean Silva On Mon, Aug 6, 2012 at 2:46 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: > > multiclass

That is what I currently have, I'm trying to simplify them even further since my multiclass file is enormous because of the amount of combinations. I have things like this: multiclass instmcRegImm<...> { def rr: inst<...>; def ri: inst<...>; def ir: inst<...>; def ii: inst<...>; } multiclass instmc<...> { defm i8 : instmcRegImm<...>; ^-- repeat for 15

On Tue, Jun 29, 2010 at 12:16 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I'm working on intrinsics for my backend and require intrinsic overloading. > Is this supported? If so, are there any examples? Some of the ARM NEON intrinsics are overloaded. -Eli

void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, - unsigned Intrinsic) { - bool HasChain = !I.doesNotAccessMemory(); - bool OnlyLoad = HasChain && I.onlyReadsMemory(); + unsigned Intrinsic) { + // Info is set by getTgtMemInstrinsic + TargetLowering::IntrinsicInfo Info; + bool

I'm working on intrinsics for my backend and require intrinsic overloading. Is this supported? If so, are there any examples? Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100629/04db85ea/attachment.html>

If I force it to use v2f32 for my register class, it still fails with: d:\hq\main\sw\appeng\tools\hpc\opencl\compiler\llvm\test\AMDIL>TableGen. exe -gen -dag-isel -I../../include/ test.td > output GPRV2F32:v2f32:$src1 MACRO_DISTANCE_FAST_v2f32: (set GPRF32:f32:$dst, (i ntrinsic_w_chain:f32 84:iPTR, GPRV2F32:v2f32:$src0, GPRV2F32:v2f32:$src1)) TableGen.exe: In

Oops. That was premature. I think your original question was on the right track. TableGen distinguishes between known and "overloaded" types (like "llvm_anyfloat_ty" in your example). The overloaded types are numbered separately, and the argument to LLVMMatchType is an index into these overloaded types, ignoring the known types. So, in your case, the first

It seems that Tablegen is generating intrinsic ID's off by in DAGISel.inc In DAGISel.inc, I have the following pattern: int64_t CN1 = Tmp0->getZExtValue(); // Pattern: (intrinsic_w_chain:f32 103:iPTR, GPRF32:f32:$src0, GPRF32:f32:$src1, GPRF32:f32:$src2) // Emits: (MACRO_FMA_f32:f32 GPRF32:f32:$src0, GPRF32:f32:$src1, GPRF32:f32:$src2) // Pattern complexity = 8 cost

From: Villmow, Micah Sent: Tuesday, November 06, 2012 1:37 PM To: 'llvm-dev at cs.uiuc.edu' Cc: Guo, Xiaoyi Subject: Bug in SelectionDAG visitTargetIntrinsic We ran into a problem where specifying IntrNoMem was causing our instruction selection to fail with target specific intrinsics. After looking into the code and ISel debug it looks like tablegen and SelectionDAG are using different

I think a multiclass may be a better fit for what you are trying to do. In fact, this is the canonical example for multiclasses: <http://llvm.org/docs/TableGenFundamentals.html#multiclass-definitions-and-instances>. --Sean Silva On Mon, Aug 6, 2012 at 1:55 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I’m trying to find examples of the foreach pattern being used in

On Wed, Jun 20, 2012 at 3:40 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > Possible to add a test case? I am not really sure what I would check. At first, I thought to add a testcase to test/TableGen; as this patch does not modify tablegen, it doesn't make sense. What kind of test should I write for this? The test should be a tablegen file that includes

Here's another question. It's failing on a clean checkout, so what does llvm use from a previous install that I would need to clean when installing a new clean checkout? On Tue, Sep 11, 2012 at 3:27 PM, Villmow, Micah <Micah.Villmow at amd.com>wrote: > Usually it is the ones that end in ".inc".**** > > ** ** > > *From:* llvmdev-bounces at cs.uiuc.edu

On Apr 15, 2009, at 11:15 AM, Villmow, Micah wrote: > I still think there is a bug somewhere, but not sure where yet. > This is what is generated in intrinsic.gen: > case Intrinsic::opencl_math_fdistance: // > llvm.opencl.math.fdistance > ResultTy = Type::FloatTy; > ArgTys.push_back(Tys[0]); > ArgTys.push_back(Tys[0]); > break; OK. That looks right to me.

That's a bug. I'm working on a fix.... On Apr 15, 2009, at 10:16 AM, Villmow, Micah wrote: > In IntrinsicEmitter::EmitTypeGenerate, called from > IntrinsicEmitter::EmitGenerator, here > for (unsigned j = 0; j != N; ++j) { > OS << " ArgTys.push_back("; > EmitTypeGenerate(OS, ParamTys[j], ArgNo); > OS << ");\n"; > }