similar to: [LLVMdev] Call Graph Analysis and function cloning

Hi Ali, I assume this is primarily for interrupt function handling? If so, I have a few ideas to bounce your direction if you're interested. -j On Aug 6, 2009, at 3:32 PM, Alireza.Moshtaghi at microchip.com wrote: > I need to perform call graph analysis (after all modules are merged) > to > find which function calls which, and depending on the attributes that > each

I am trying to verify the generated DAG after converting from llvm to DAG, however I'm not sure if this is correct or not. Here is the situation: In order to get LLVM to lower to 8-bit I have to define only 8-bit registers and the pointer size also to be 8-bit. Doing so, the attached DAG is generated for a load:i16. I have problem understanding this DAG in two places: 1)As you can see the

Attached please find the gdb backtrace dump and the postscript file of the DAG right before assertion. The red Node is the current Node in LegalizeOp() The only thing that I am customizing before we get here is the FORMAL_ARGUMENTS. At this time I don't really care about the arguments, just want to get some global values working. When I trace the program, it is well passed the legalizing of

Jim Grosbach wrote: > Hi Ali, > > Thanks for bringing this up. You're definitely under very tight design > constraints from the hardware. I can certainly sympathize. Jim, First of all, thank you very much for understanding every detail of the problem at our hand and coming up with a solution that addresses every aspect of it. IMO, given the constraints, this is probably the best

Any thoughts on this? I would like to get it right before jumping into the nuts and bolts of it.... Thanks ________________________________ From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Alireza.Moshtaghi at microchip.com Sent: Thursday, March 12, 2009 10:39 AM To: llvmdev at cs.uiuc.edu Subject: RE: [LLVMdev] promotion of return value.

This method is defined in: Lib/VMCore/Type.cpp And it makes hard assumption that size of integer is 32 or 64. This gives us trouble because we have 16 bit integer. Is there a reason for this assumption? Or we can just add the 16-bit integer to it as well? Thanks Alireza Moshtaghi Senior Software Engineer Development Systems, Microchip Technology

Thank you Chris, That is great news... So his modifications are in llvm-2.2? How has Christopher tested them? Are there attributes or intrinsics that I can also use? A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Chris Lattner Sent: Tuesday, January 29, 2008 9:23 PM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] C

Below I have pasted the latest design that we discussed... Now we would like to pick it up and do the implementation. 1) Is there any last change that we would like to add? 2) Has anyone been working on it? I haven't seen any thing new in the code so I assume the answer is no... Thanks Alireza Moshtaghi Senior Software Engineer Development Systems, Microchip Technology Subject: Troubling

Chris, Extending LLVM IR to support PointerTypes that take an address space is what I was hoping to avoid. However, if we want to do things right, that is probably the way to go. Now that we got here, let me write some of my thoughts on this and solicit your input: --- 1) Syntax extension: In our existing compiler for 8-bit microcontrollers, we have introduced rom and ram qualifiers (with ram

On Sep 28, 2007, at 1:10 PM, <Alireza.Moshtaghi at microchip.com> <Alireza.Moshtaghi at microchip.com> wrote: > Attached please find the gdb backtrace dump and the postscript file of > the DAG right before assertion. > The red Node is the current Node in LegalizeOp() Okay, this is the problem. LegalizeOp should only be called on a node if the VT is valid for the target.

On May 28, 2008, at 11:53 AM, <Alireza.Moshtaghi at microchip.com> <Alireza.Moshtaghi at microchip.com > wrote: >> Ok. We already have this, with the 'signext' attribute. This code: >> >> signed char g(); >> signed char foo(){ >> return g(); >> } >> >> compiles into: >> >> define i8 @foo() signext nounwind {

So does that mean that LLVM can't lower automatically to 8-bit values? I tried defining 8-bit pointers in the subtarget using "p:8:8:8" but it asserts at line 566 of TargetData.cpp in the default case of TargetData::getIntPtrType() Is it difficult to add 8-bit support? A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On

On Oct 8, 2007, at 3:15 PM, Alireza.Moshtaghi at microchip.com wrote: > I am trying to verify the generated DAG after converting from llvm to > DAG, however I'm not sure if this is correct or not. > Here is the situation: > In order to get LLVM to lower to 8-bit I have to define only 8-bit > registers and the pointer size also to be 8-bit. > Doing so, the attached DAG is

Thank you Evan, I added the return Type::Int8Ty to the switch statement to get it to work. I don't know if this can have other consequences, I haven't yet verified if the generated Legalized DAG is correct though. A. -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Monday, October 01, 2007 3:23 PM To:

Evan, The machine is 8 bit, and of course all registers are 8-bit too. Memory access on this machine is a bit different. The memory is banked into banks of 256-byte, and you can select the active bank using a bank select register. All instructions can access the memory with an 8-bit operand, so in that sense the address space can be viewed as 256-byte long. On the other hand, there are three

Christopher, Thank you for all the work :-) Regarding the regression testing, it is in our plan to contribute into LLVM. The current state of our project is not in the form that we can do this at this time though, but I'm hoping that we can get some minimal functionality into LLVM before LLVM 2.3 (at most LLVM 2.4) release. Looks like you have also (at least on your local project) taken

Previously we talked about adding new attributes to function to identify the promotion class. > sign_ext_from_i8, sign_ext_from_i16 > zero_ext_from_i8, zero_ext_from_i16 Aren't these attributes more applicable to return value? of course then the question would be if they are also applicable to parameters too? (because we use same attributes for parameters and return value)? or

But they both follow the same calling convention. There are two possibilities in the caller: 1) Call node returns sizeof(int) or larger: in this case there is no truncation. 2) Call node returns smaller than sizeof(int): in this case callee always has to return an int so it has to consistently either sign extend or zero extend because int is either signed or unsigned consistently for that port.

Hi, I have started to write an llvm backend for one of our microcontrollers (PICxx). I started studying the framework of PowerPc backend of llvm and decided to start by following that framework. Now I have most of the classes and Tblgen files written for a very basic hypothetical microcontroller with very few instructions. The project builds and the llc recognizes the new processor, however,

ExpandOp is not called at all. In SelectionDAGLegalize::HandleOp() only the ValueType is considered in the switch statement to decide if it is legal or promote or expand. As I trace back (correct me if I'm wrong) these values are set in TargetLowering::computeRegisterProperties() and it is based on the largest register class (in my case the smallest possible pointer size, 16-bit) So it reduces