similar to: [LLVMdev] Methods for filing delay slots.

On Sun, Aug 2, 2009 at 2:06 PM, Carter Cheng<carter_cheng at yahoo.com> wrote: > I was looking over the experimental MIPS backend and noticed that it has a delay slot pass which just inserts nops into the delay slots. I assume it should be possible to do a bit better than this. Is there an existing pass which "fills" delay slots or would I have to write one if I wanted slightly

The Sparc, Microblaze, and Mips code generators implement branch delay slots. They all seem to exhibit the same bug, which is not surprising since the code is very similar. If I compile code with this snippit: while (n--) *s++ = (char) c; I get this (for the Microblaze): swi r19, r1, 0 add r3, r0, r0 cmp r3, r3, r7 beqid r3,

On Dec 14, 2010, at 3:46 PM, Richard Pennington wrote: > Notice that the label $BB0_1 is missing. If I disable filling in the > branch delay slots, I get: Is this with the latest SVN HEAD version of LLVM or some other version? The delay slot filler and many other things have been updated for the Microblaze backend. In particular, the commit r120095 for the MBlaze backend fixed some issues

Hello. I am progressing a bit with difficulty with the post RA scheduler (PostRASchedulerList.cpp with ScoreboardHazardRecognizer) - the problem I have is that it doesn't advance at the next available instruction when the overridden ScoreboardHazardRecognizer::getHazardType() method returns NoopHazard and it gets stuck at the same instruction (store in my runs). Just to make sure:

Hello. Hal, thank you for the information. I managed to get inspired from PPCHazardRecognizers.cpp. So I created my very simple [Target]HazardRecognizers.cpp pass that is also derived from ScoreboardHazardRecognizer. My class only implements the method getHazardType(), which checks if, as stated in my first email, for example, I have a store instruction that is storing the value

On 12/14/2010 04:28 PM, Wesley Peck wrote: > On Dec 14, 2010, at 3:46 PM, Richard Pennington wrote: >> Notice that the label $BB0_1 is missing. If I disable filling in the >> branch delay slots, I get: > > Is this with the latest SVN HEAD version of LLVM or some other version? The delay slot filler and many other things have been updated for the Microblaze backend. In

Hello. Hal, the problem I have is that it doesn't advance at the next available instruction - it always gets the same store. This might be because I did not specify in a file like [Target]Schedule.td the functional units, processor and instruction itineraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the

Hello. I see there is little information on specifying instructions with delay slots. So could you please tell me how can I insert NOPs (BEFORE or after an instruction) or how to make an aware instruction scheduler in order to avoid miscalculations due to the delay slot effect? More exactly, I have the following constraints on my (SIMD) processor: - certain stores or

Hi, in section B.29. (Write State Register Instructions) of 'The SPARC Architecture Manual Version 8' it is said that the "The write state register instructions are delayed-write instructions." The Y-register is a state-register. Furthermore in the B.29-secion there is a programming note saying: MULScc, RDY, SDIV, SDIVcc, UDIV, and UDIVcc implicitly read the Y register.

Hello, I am trying to improve lib/Target/Mips/MipsDelaySlotFiller.cpp by substituting nops emitting with instructions reordering. I need a hazard recognizer, but I haven't found any. Do I have to create one, or looking bad and there is any? Thanks for any reply. -- Filip Kocina, student FIT Email: xkocin00 at stud.fit.vutbr.cz

I am curious- what is the current status of the MIPS support in LLVM? I have a mipsel device and was wondering if I could compile code for it with clang. Would I have to implement a backend setup myself? Is there also an option to compile w/ clang on an x86 for Mipsel? Thanks in advance.

Hi Filip, > I am trying to improve lib/Target/Mips/MipsDelaySlotFiller.cpp by > substituting nops emitting with instructions reordering. I need > a hazard recognizer, but I haven't found any. Do I have to create > one, or looking bad and there is any? You have to create one! Take a look at PPCHazardRecognizers.cpp and SPUHazardRecognizers.cpp for examples. If you can, contribute

This is probably another very basic question- but is there a simple method for cross compiling LLVM for another platform? Thanks in advance.

Dear All, I'm enhancing a MachineFunctionPass that enforces control-flow integrity. One of the things I want to do is to set the alignment of an instruction (by adding NOPs before it in the MachineBasicBlock or by emitting an alignment directive to the assembler) if it causes a specific sequence of bytes to be generated at a specific alignment. The goal is to ensure that sequences of

Hi Anton, I ran llc with -verify-coalescing. There were no error messages. Then I added code in MipsPassConfig::addPreEmitPass() to prevent machine verifier from running post delay -slot-filler, and ran llc again. Again, there were no error messages. This is the list of passes run after post-RA scheduling. machine verifier is run twice after post RA scheduler (and CriticalAntiDepBreaker) is run.

On 12/14/2010 04:32 PM, Richard Pennington wrote: > On 12/14/2010 04:28 PM, Wesley Peck wrote: >> On Dec 14, 2010, at 3:46 PM, Richard Pennington wrote: >>> Notice that the label $BB0_1 is missing. If I disable filling in the >>> branch delay slots, I get: >> >> Is this with the latest SVN HEAD version of LLVM or some other version? The delay slot filler and

I have been toying around with the LLVM tutorial code and I am trying to deduce what I can from it as a basis for a compiler frontend for a simple language of my own devising (once I understand what I am doing I will probably attempt mapping a more complex language target). I am having some difficulties however understanding how certain things work and I was hoping perhaps someone could help me

I want to be able to do two things with LLVM (both just before code emission): 1. Insert a MachineBasicBlock just before a MachineBasicBlock. There is a function called AddPredecessor(). However, the comment says that it does not update the actual CFG. I want to redirect all CFG edges that are incoming to this MachineBasicBlock to the new one I create, and add just one outgoing edge (no branch)

Thanks both. I looked over the getelementptr and bitcast documentation but I am still a bit confused by one point. lets say i have something like this. union { long Int; double float; long* IntRef; } Since pointer sizes are platform dependent if I am trying to use the union in question with an extern C function is it possible to make write the single definition in a platform independent way?

Hi all, My understanding is that we keep around KILL instructions in order to keep the results of the various register liveness analysis passes valid. Consider for example the following machine basic block: BB#0: derived from LLVM BB %entry Live Ins: %A0_64 %A1_64 %V0_64<def> = AND64 %A0_64<kill>, %A1_64<kill> %V0<def> = KILL %V0,