similar to: [LLVMdev] Two Regalloc Enhancements

On Jul 23, 2009, at 12:42 PM, David Greene wrote: > We have two features for register allocation we'd like to contribute > if folks > think they are worthwhile. We want to get a read on whether they > will be > useful to people. > > The first features backschedules reloads during the spilling phase. > As > reloads are generated, we have some very simple code

Hi David, What effect is there on compile time? David Greene wrote: > We have two features for register allocation we'd like to contribute if folks > think they are worthwhile. We want to get a read on whether they will be > useful to people. > > The first features backschedules reloads during the spilling phase. As > reloads are generated, we have some very simple

On Thursday 23 July 2009 18:07, Evan Cheng wrote: > Ok. As with any heuristics change, some tests will benefit, some will > suffer. I am ok with both sets of changes assuming there are ways to > control them. Yep, we have flags. > Post-ra scheduling has been working for a while. The reason it's not > turned on for x86 is it's not helping much (1 or 2%) while the compile

Hi again, Now, after I fixed the graph coloring regalloc bug that was triggered by the ARM target, I continue testing and found another bug, this time on the XCore target. First I thought that it is again specific to my register allocator, but it seems to be trigerred also by LLVM's linearscan register allocator. I don't know if the XCore target is stable enough in LLVM, or may be I

Roman Levenstein wrote: > Hi again, > > Now, after I fixed the graph coloring regalloc bug that was triggered > by the ARM target, I continue testing and found another bug, this time > on the XCore target. First I thought that it is again specific to my > register allocator, but it seems to be trigerred also by LLVM's > linearscan register allocator. > > I don't

Hi Quentin, MyInst is a custom instruction that has implicit-defs of fixed registers. The implicit-defs are seen at the end of Instruction Selection. I'd like to add a report, but I am working on an out-of-tree backend based on 7.0. I can try to help reduce the testcase down. Filed https://bugs.llvm.org/show_bug.cgi?id=41790 Regards, Kevin On 2019-05-07 3:45 p.m., Quentin Colombet wrote:

On Jan 13, 2009, at 11:20 AM, Richard Osborne <richard at xmos.com> wrote: > Roman Levenstein wrote: >> Hi again, >> >> Now, after I fixed the graph coloring regalloc bug that was triggered >> by the ARM target, I continue testing and found another bug, this >> time >> on the XCore target. First I thought that it is again specific to my >>

Hi people, the LinearScan register allocator tries to use same register for both live intervals, if the new interval is defined by a register copy whose destination reg is compatible with the source register. This is ok. However, this "check for compatibility" is wrongly done IMHO. Say I have regclass1 with reg A, and regclass2 with regs {A, B}, but regclass2 defines only

On Wed, Apr 21, 2004 at 11:01:48AM +0200, Finn S Andersen wrote: > For some of the benchmarks the linear scan regalloc > works. When it does, results are in the x1.0 - 1.5 > range. Unfortunately, the linear scan allocator breaks > on most of my code. Is there a chance you can try cvs? I would be interested to get a simplified test case where the allocator breaks. A lot of

Hello, On Fri, Nov 14, 2008 at 6:57 PM, H. Johnson <misc at faradayco.com> wrote: > llc -march=x86 tempfileB.bc yields: > llc: for the -march option: : Cannot find option named 'x86'! Run llc -help and see, if any backends were linked in. It will show you list of all backends, which were 'registered' and thus known to llc. -- With best regards, Anton Korobeynikov

Hi, I have a question about x86 code quality. I have run a few benchmarks and compared the running time of executables created by LLVM to executables created by gcc. It appears that code generated by LLVM is x1.5 - x3 times slower than code generated by gcc, for the x86 For some of the benchmarks the linear scan regalloc works. When it does, results are in the x1.0 - 1.5 range. Unfortunately,

Alkis Evlogimenos wrote: >Is there a chance you can try cvs? I would be interested to >get a simplified test case where the allocator breaks. A lot of >improvements went into the x86 backend since 1.2 and we currently have >no test cases where the allocator breaks today. > > I updated and recompiled and the error is still there. It turns out that I cannot use the bugpoint

llc -march=x86 tempfileB.bc yields: llc: for the -march option: : Cannot find option named 'x86'! Windows build using Visual Studio 2008 Express with CMake. clang and other tools seem to also complain about the format of -march, but other command line arguments seem to be working. Tools, clang llvm-as, opt, etc., "seem" to be working. Incidently, the bytecode file was

Hi Prasad, The comments at the beginning of RegAllocPBQP.cpp list the two most relevant papers for PBQP register allocation. // (1) Hames, L. and Scholz, B. 2006. Nearly optimal register allocation with // PBQP. In Proceedings of the 7th Joint Modular Languages Conference // (JMLC'06). LNCS, vol. 4228. Springer, New York, NY, USA. 346-361. // // (2) Scholz, B., Eckstein, E.

Hello, we are currently working on my project that aims at improving the register allocation scheme by identifying if the interference graphs are chordal or not. we are working on the llvm compiler .we are forcing the compiler to use PBQP register allocation scheme by an option of ' ' regalloc=pbqp ' during the execution of prgm. we have been succesfull in accessing the interference

On Sep 13, 2010, at 6:59 AM, Carlos Sánchez de La Lama wrote: > Hi people, > > the LinearScan register allocator tries to use same register for both > live intervals, if the new interval is defined by a register copy > whose destination reg is compatible with the source register. This is > ok. However, this "check for compatibility" is wrongly done IMHO. >

Sorry to disturb you all, but I simply cannot get the linearscan allocator to work. I have upgraded llvm to mainline cvs. Everything works until I get to llc -regalloc=linearscan or lli -regalloc=linearscan. I have installed it on redhat 9 and on Fedora Core distributions (I even took it as far as to format a new partition and install Fedora core all over). I have submitted the bytecode that

Chris Lattner wrote: >I can't reproduce this failure with mainline CVS using either lli or llc: > >$ lli -regalloc=linearscan a.out.bc >$ echo $status >0 > >Are you sure that the CVS version is in your path? > > After configure and make I run make install, which moves the executables to /usr/local/bin, right ? And yes, they are in my path. But thank you very

Hi! I developed a register allocator within LLVM and now I need to test its efficiency. Can I do this using llvm-test package? Do llvm tests check all available regalloc options automatically? If not, then what modifications should I do to the test files? It would be great if I could test my algo along with linearscan and compare the results. Thanks. Tony. -- "Nae king! Nae quin! Nae

On 11/23/07, Fernando Magno Quintao Pereira <fernando at cs.ucla.edu> wrote: > > > Hi, Sanjiv, > > those passes operate on the whole machine function. Each machine > function contains many basic blocks. If a program has many functions, the > register allocator will be called as many times, i.e it does not do > interprocedural allocation. > > best, > >