similar to: [LLVMdev] Help: Instruction Pattern Matching question

On Fri, 2012-09-14 at 13:10 -0500, Will Schmidt wrote: > Hi all, > > I've been poking at AsmParser support for powerpc64 > (ppc64-elf-linux-abi) and have run into some behavior I don't understand > with the ptr_rc references coming out of the PPC*.td files when > generating the asm-matcher files. > > For instance : > $ ./build/bin/llvm-tblgen

Hi all, I've been poking at AsmParser support for powerpc64 (ppc64-elf-linux-abi) and have run into some behavior I don't understand with the ptr_rc references coming out of the PPC*.td files when generating the asm-matcher files. For instance : $ ./build/bin/llvm-tblgen llvm/lib/Target/PowerPC/PPC.td -I ~/llvm-head/llvm/include -I ~/llvm-head/llvm/lib/Target/PowerPC/ -gen-asm-matcher

What does MIOperandInfo exactly mean while defining an Operand class? e.g. here class X86MemOperand<string printMethod> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm); } -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi! I'm writing a new back-end for a new architecture. First, I'll do some "tests" with an existing back-end (I chose the Sparc back-end). My architecture has special address-registers and I want to add such new address-registers to my Sparc back-end. 1) I defined a new register call AddrRegs 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) 3) I

Hello, I'm trying to define in my new back end, in MyBackendInstrInfo.td file, a vector load instruction that takes an immediate address operand. (I got inspired from Mips' MSA SIMD extensions.) Could you please tell me what's the right way to do it? Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class

Hi, I want to encode Loongson ISA initially https://gist.github.com/xiangzhai/8ae6966e2f02a94e180dd16ff1cd60ac gslbx           $2,0($3,$4) It is equivalent to: dadd $1, $3, $4 lb $2,0($1) I just use  mem_simmptr  as the default value of  DAGOperand MO , because  MipsMemAsmOperand  use  parseMemOperand  to parse general  MemOffset  and only *one*  AnyRegister , for example: 0($1) But 

On Wed, 2012-09-19 at 18:41 -0500, Will Schmidt wrote: > On Fri, 2012-09-14 at 13:10 -0500, Will Schmidt wrote: > > Hi all, > > > > I've been poking at AsmParser support for powerpc64 > > (ppc64-elf-linux-abi) and have run into some behavior I don't understand > > with the ptr_rc references coming out of the PPC*.td files when > > generating the

On 9/25/07, Evan Cheng <evan.cheng at apple.com> wrote: > > Hi Evan, > > wouldn't this generate fairly terrible code if each address register > > use has to be preceded by instructions to make an address register > > hold the right value? > > No. I would suggest doing this as a instruction selection post pass. > It would operate on DAGs so you still get

On Sep 24, 2007, at 1:12 AM, Andreas Fredriksson wrote: > On 9/24/07, Evan Cheng <evan.cheng at apple.com> wrote: > >> I am going to suggest something shocking. :) Since you will end up >> writing a >> bunch of target specific code anyway, you might a well write a target >> specific pass that change generic instructions into data register >> variant

On Oct 19, 2007, at 8:15 AM, Boris Boesler wrote: > Hi! > > I'm writing a new back-end for a new architecture. First, I'll do > some "tests" with an existing back-end (I chose the Sparc back-end). > My architecture has special address-registers and I want to add such > new address-registers to my Sparc back-end. > > 1) I defined a new register call

On Nov 15, 2012, at 2:54 PM, Will Schmidt <will_schmidt at vnet.ibm.com> wrote: > > Can anyone confirm or deny tablegen supporting PointerLikeRegClass? X86 is using it. You could start by determining what PPC is doing differently. /jakob

I'm trying to create new backend. Can anyone help with such question? In a target there are 32 and 64-bit registers. I've made load/store 32-bit values without difficulties. Now i'm doing 64-bit store into memory. There is a direct 64bit store of register -> memory (i represented it in TargetInstructionInfo.td) and wrote lowering for i64 Constant store. The question is: does

Hi Alex, So far, the code you've mentioned only defines a couple tablegen classes but doesn't define the instruction itself. To define the instruction you will also need a 'def' statement. For MIPS MSA, this statement looks like this: def LD_D: LD_D_ENC, LD_D_DESC; This defines an instruction (LD_D) with the encoding specified by the LD_D_ENC class, and the operation

Hi, I'd like to subscribe folder with doveadm: doveadm mailbox subscribe -u rago public.Conferences This command doesn't work, while it works with an ordinary folder. However it's possible to subscribe to the folder with an imap connection: 1 login rago "mypasswd" 1 OK [CAPABILITY IMAP4rev1 LITERAL+ SASL-IR LOGIN-REFERRALS ID ENABLE IDLE SORTSORT=DISPLAY

On Sep 29, 2007, at 2:57 PM, Andreas Fredriksson <deplinenoise at gmail.com> wrote: > On 9/25/07, Evan Cheng <evan.cheng at apple.com> wrote: >>> Hi Evan, >>> wouldn't this generate fairly terrible code if each address register >>> use has to be preceded by instructions to make an address register >>> hold the right value? >> >>

Hi all, I'm interested in obtaining the cycles spend by the CPU from LLVM and i was wondering if this was possible to obtain this with the scheduling information from LLVM. (For the cortex-m0 in particular). I found the following function : getInstrLatency() in the TargetInstrInfo class. If i sum the latencies of the instructions in a basic block i suppose i will get the total cycle cost