Displaying 20 results from an estimated 5000 matches similar to: "[LLVMdev] LLVM on 64-bit PowerPC Linux"
2008 Jul 08
3
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Evan,
Evan Cheng wrote:
> The patch looks great. But I do have one comment:
>
> +let usesCustomDAGSchedInserter = 1 in {
> + let Uses = [CR0] in {
> + let Uses = [R0] in
> + def ATOMIC_LOAD_ADD_I32 : Pseudo<
>
> The "let Uses = [R0]" is not needed. The pseudo instruction will be
> expanded like this later:
>
> + BuildMI(BB,
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Look for createVirtualRegister. These are examples in
PPCISelLowering.cpp.
Evan
On Jul 8, 2008, at 8:24 AM, Gary Benson wrote:
> Hi Evan,
>
> Evan Cheng wrote:
>> The patch looks great. But I do have one comment:
>>
>> +let usesCustomDAGSchedInserter = 1 in {
>> + let Uses = [CR0] in {
>> + let Uses = [R0] in
>> + def ATOMIC_LOAD_ADD_I32 :
2008 Jul 08
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Would it be acceptable to change MachineInstr::getRegInfo from private
to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter?
Cheers,
Gary
Evan Cheng wrote:
> Look for createVirtualRegister. These are examples in
> PPCISelLowering.cpp.
>
> Evan
> On Jul 8, 2008, at 8:24 AM, Gary Benson wrote:
>
> > Hi Evan,
> >
> > Evan Cheng wrote:
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Cool, that worked. New patch attached...
Cheers,
Gary
Evan Cheng wrote:
> Just cast both values to const TargetRegisterClass*.
>
> Evan
>
> On Jul 10, 2008, at 7:36 AM, Gary Benson wrote:
> > Evan Cheng wrote:
> > > How about?
> > >
> > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
> > > &PPC:G8RCRegClass;
>
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Evan Cheng wrote:
> How about?
>
> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
> &PPC:G8RCRegClass;
> unsigned TmpReg = RegInfo.createVirtualRegister(RC);
I tried something like that yesterday:
const TargetRegisterClass *RC =
is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass;
but I kept getting this error no matter how I arranged it:
2008 Jun 30
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Chris Lattner wrote:
> On Jun 27, 2008, at 8:27 AM, Gary Benson wrote:
> > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:
> > $label),
> > "cmpw $rA, $rB\n\tbne- La${label}_exit",
> > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm:
> > $label)]>;
> > }
> >
> > ...and
2008 Jul 11
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Evan,
Evan Cheng wrote:
> This does not patch cleanly for me (PPCISelLowering.cpp). Can you
> prepare a updated patch?
This should work, though I won't have access to my test box now until
next Thursday so no guarantees :)
Cheers,
Gary
--
http://gbenson.net/
-------------- next part --------------
Index: lib/Target/PowerPC/PPCISelLowering.h
2008 Jul 10
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Just cast both values to const TargetRegisterClass*.
Evan
On Jul 10, 2008, at 7:36 AM, Gary Benson wrote:
> Evan Cheng wrote:
>> How about?
>>
>> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
>> &PPC:G8RCRegClass;
>> unsigned TmpReg = RegInfo.createVirtualRegister(RC);
>
> I tried something like that yesterday:
>
> const
2008 Jul 09
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Ah, didn't see that, that's what comes of trying to do something at
5pm :) I attached an updated patch which creates a virtual register
instead of using R0. How does this look?
Cheers,
Gary
Dan Gohman wrote:
> PPCTargetLowering::EmitInstrWithCustomInserter has a reference
> to the current MachineFunction for other purposes. Can you use
> MachineFunction::getRegInfo instead?
2008 Aug 22
3
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
No, I don't.
Cheers,
Gary
Dale Johannesen wrote:
> This looks OK to check in, do you have write access?
>
> On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote:
>
> >Dale Johannesen wrote:
> >>On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote:
> >>>I'm trying to implement llvm.memory.barrier on PowerPC. I've
> >>>modelled my patch
2008 Jul 11
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Gary,
This does not patch cleanly for me (PPCISelLowering.cpp). Can you
prepare a updated patch?
Thanks,
Evan
On Jul 10, 2008, at 11:45 AM, Gary Benson wrote:
> Cool, that worked. New patch attached...
>
> Cheers,
> Gary
>
> Evan Cheng wrote:
>> Just cast both values to const TargetRegisterClass*.
>>
>> Evan
>>
>> On Jul 10, 2008, at 7:36
2008 Jul 25
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
Hi all,
I want to implement llvm.memory.barrier on PowerPC. The
implementation would be the single instruction "sync", but
currently it's defined with:
setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand)
in lib/Target/PowerPC/PPCISelLowering.cpp, which causes it
to be a noop. I replaced the "Expand" with "Legal" in the
hope I'd get an error message
2008 Jun 30
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
You need to insert new basic blocks and update CFG to accomplish this.
There is a hackish way to do this right now. Add a pseudo instruction
to represent this operation and mark it usesCustomDAGSchedInserter.
This means the intrinsic is mapped to a single (pseudo) node. But it
is then expanded into instructions that can span multiple basic
blocks. See
2008 Aug 21
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
Dale Johannesen wrote:
> On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote:
> > I'm trying to implement llvm.memory.barrier on PowerPC. I've
> > modelled my patch (attached) on the implementation in X86, but
> > when I try and compile my test file (also attached) with llc I
> > get the error "Cannot yet select: 0x10fa4ad0: ch = MemBarrier
> >
2008 Aug 21
0
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
This looks OK to check in, do you have write access?
On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote:
> Dale Johannesen wrote:
>> On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote:
>>> I'm trying to implement llvm.memory.barrier on PowerPC. I've
>>> modelled my patch (attached) on the implementation in X86, but
>>> when I try and compile my test
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
PPCTargetLowering::EmitInstrWithCustomInserter has a reference
to the current MachineFunction for other purposes. Can you use
MachineFunction::getRegInfo instead?
Dan
On Jul 8, 2008, at 1:56 PM, Gary Benson wrote:
> Would it be acceptable to change MachineInstr::getRegInfo from private
> to public so I can use it from
> PPCTargetLowering::EmitInstrWithCustomInserter?
>
>
2008 Jul 02
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Evan Cheng wrote:
> You need to insert new basic blocks and update CFG to accomplish this.
> There is a hackish way to do this right now. Add a pseudo instruction
> to represent this operation and mark it usesCustomDAGSchedInserter.
> This means the intrinsic is mapped to a single (pseudo) node. But it
> is then expanded into instructions that can span multiple basic
>
2008 Jun 27
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi all,
I'm trying to figure out how to add the instructions required for
llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch
attached) but the other two (CMP_UNRESw and STWCX) require multiple
instructions:
let Defs = [CR0] in {
def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label),
"stwcx. $rS, $dst\n\tbne-
2008 Jul 12
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Committed. Thanks!
Evan
On Jul 11, 2008, at 1:07 PM, Gary Benson wrote:
> Hi Evan,
>
> Evan Cheng wrote:
>> This does not patch cleanly for me (PPCISelLowering.cpp). Can you
>> prepare a updated patch?
>
> This should work, though I won't have access to my test box now until
> next Thursday so no guarantees :)
>
> Cheers,
> Gary
>
> --
>
2008 Aug 19
2
[LLVMdev] Implementing llvm.memory.barrier on PowerPC
Hi all,
I'm trying to implement llvm.memory.barrier on PowerPC. I've modelled
my patch (attached) on the implementation in X86, but when I try and
compile my test file (also attached) with llc I get the error "Cannot
yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68,
0x10fa4be0, 0x10fa4be0, 0x10fa4be0, 0x10fa4be0". This presumably
means my "membarrier"