Displaying 20 results from an estimated 8000 matches similar to: "[LLVMdev] simulating c style unions in LLVM"
2009 Jun 30
0
[LLVMdev] simulating c style unions in LLVM
2009/6/29 Carter Cheng <carter_cheng at yahoo.com>:
>
> I am trying to create a boxed tagged datatype for a language where it is necessary to resolve the type at runtime. If I were writing an interpreter in C- it would most likely look something like this-
>
> Is there a standard way for constructing a type like this in LLVM?
>
Well, you can always ask bitter melon, who
2009 Jun 30
2
[LLVMdev] simulating c style unions in LLVM
Thanks both. I looked over the getelementptr and bitcast documentation but I am still a bit confused by one point. lets say i have something like this.
union
{
long Int; double float; long* IntRef;
}
Since pointer sizes are platform dependent if I am trying to use the union in question with an extern C function is it possible to make write the single definition in a platform independent way?
2009 Jun 30
0
[LLVMdev] simulating c style unions in LLVM
On Tue, Jun 30, 2009 at 12:16 AM, Carter Cheng<carter_cheng at yahoo.com> wrote:
> Since pointer sizes are platform dependent if I am trying to use the union in question with an extern C function is it possible to make write the single definition in a platform independent way?
Not really; there's some discussion of that in the thread starting at
2009 Jun 30
1
[LLVMdev] simulating c style unions in LLVM
Eli Friedman wrote:
> On Tue, Jun 30, 2009 at 12:16 AM, Carter Cheng<carter_cheng at yahoo.com> wrote:
>
>> Since pointer sizes are platform dependent if I am trying to use the union in question with an extern C function is it possible to make write the single definition in a platform independent way?
>>
>
> Not really; there's some discussion of that in
2009 Jun 02
2
[LLVMdev] Request to Bitter Melon regarding the LLVM demo page
Hi Bitter Melon!
If it's not too much trouble, could you add a check box to the LLVM demo
page to pass the -fnested-functions option to llvm-gcc? I'm interested
in studying how nested functions are implemented, but haven't yet been
able to get llvm-gcc built on my own system.
Thanks!
Eric
2009 Jun 02
0
[LLVMdev] Request to Bitter Melon regarding the LLVM demo page
Hi Eric,
> If it's not too much trouble, could you add a check box to the LLVM demo
> page to pass the -fnested-functions option to llvm-gcc? I'm interested
> in studying how nested functions are implemented, but haven't yet been
> able to get llvm-gcc built on my own system.
I turned it on unconditionally. Meow!
Bitter Melon.
2010 Jan 15
3
[LLVMdev] [PATCH] - Union types, attempt 2
2010/1/14 Talin <viridia at gmail.com>:
> The reason for doing it this way is that to construct a union, you really
> need 4 pieces of information: The type of the union, the type and value of
> the member to be initialized, and the index of which member is being
> initialized.
Does requiring the index mean that uniquing the union type will have
to re-write many of the
2010 Jan 15
0
[LLVMdev] [PATCH] - Union types, attempt 2
On Thu, Jan 14, 2010 at 9:25 PM, me22 <me22.ca at gmail.com> wrote:
> 2010/1/14 Talin <viridia at gmail.com>:
> > The reason for doing it this way is that to construct a union, you really
> > need 4 pieces of information: The type of the union, the type and value
> of
> > the member to be initialized, and the index of which member is being
> >
2009 Aug 02
2
[LLVMdev] Union type efforts and ComputeLinearIndex
I just looked over your diff and it would seem to me that additional changes would be needed to be done to some of the LLVM-IR -> DAG stuff to make things fully functional (this could be a bit of supposition on my part since I do not fully understand all of the code).
--- On Sun, 8/2/09, Andrew Lenharth <andrewl at lenharth.org> wrote:
> From: Andrew Lenharth <andrewl at
2010 Jan 15
1
[LLVMdev] [PATCH] - Union types, attempt 2
2010/1/15 Talin <viridia at gmail.com>:
> On Thu, Jan 14, 2010 at 9:25 PM, me22 <me22.ca at gmail.com> wrote:
>>
>> @foo = constant union { float, i32 } insertvalue union { i32,
>> float } undef, i32 4, 0
>> @bar = constant union { i32, float } insertvalue union { float,
>> i32 } undef, i32 4, 1
>>
>
> Well, the fact that union members
2009 Aug 02
0
[LLVMdev] Union type efforts and ComputeLinearIndex
On Sun, Aug 2, 2009 at 6:09 PM, Carter Cheng<carter_cheng at yahoo.com> wrote:
> I just looked over your diff and it would seem to me that additional changes would be needed to be done to some of the LLVM-IR -> DAG stuff to make things fully functional (this could be a bit of supposition on my part since I do not fully understand all of the code).
Code generation actually was
2006 Mar 24
2
Return all rows, split then show uniques
I''m returning some rows from a tags database that look like this:
ID WORDS
1. apple banana pear
2. banana melon
3. apple peach lime
What I want to do with that data is use the .split method to divide them
into separate values in an array, then use the .uniq method to return a
unique list of the words like so:
apple, banana, pear, melon, peach, lime
So in my controller I
2014 Dec 15
4
[LLVMdev] ubsan - active member check for unions
Hi,
I decided to implement a sanitizer that tracks the active member, and
reports reads from inactive members.
e.g.:
struct S {
union {
long l;
char s[42];
double d;
};
};
void f() {
S s;
s.d = 42.0;
if (s.l > 100) // fire here
;
}
My current implementation is naïve (also possibly wrong), and doesn't
care about "special
2013 Nov 23
2
[LLVMdev] GVN fails with bitcasts
Hi,
i have the following code:
define internal %"struct.dexter::ConditionConstant"*
@_ZN6dexter18BinaryConditionAdd8evaluateEv5(%"class.dexter::BinaryConditionAdd"*)
{
entry:
%1 = getelementptr inbounds %"class.dexter::BinaryConditionAdd"* %0, i32
0, i32 0, i32 1
%2 = load %"class.dexter::BaseCondition"** %1, align 8
%3 = bitcast
2009 Aug 17
2
[LLVMdev] ARMSchedule.td MipsSchedule.td etc.
I apologize if this has been asked before but which classes utilize the information in these files? I am asking since I am trying to extend the MIPS backend to 64bit among other things.
Thanks in advance,
Carter.
2009 Aug 02
0
[LLVMdev] Union type efforts and ComputeLinearIndex
I posted an initial implementation that would generate code correctly,
though I don't know that all optimization pass were safe still.
see:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20090511/077443.html
As far as I know, there isn't enough demand right now for unions.
They are mainly useful for target-independent front-ends. I don't
have the time right now to push
2009 Aug 02
3
[LLVMdev] Union type efforts and ComputeLinearIndex
Hi,
I really dont know I came rather late to the discussion and some kind folks on this list gave me a few links. I didnt see much mention of any controversy. Are there issues still that need to be resolved?
So far I am still quite the novice with LLVM internals but looking over the code it looks like one could hack in most of the required functionality up to the DAG building stage. I am not
2009 Aug 18
1
[LLVMdev] ARMSchedule.td MipsSchedule.td etc.
Yes. But it is not really being used by most (any?) targets because
post-RA scheduling is disabled by default. Also, the existing model is
very limited in what types of micro-architectures can be described.
I've been extending it to enable scheduling of multi-issue targets,
targets with overlapping FU usage, and targets that use and define
registers in multiple pipeline stages.
See
2009 Jul 27
3
[LLVMdev] Current status of MIPS support (some basic questions)
I am curious- what is the current status of the MIPS support in LLVM? I have a mipsel device and was wondering if I could compile code for it with clang.
Would I have to implement a backend setup myself?
Is there also an option to compile w/ clang on an x86 for Mipsel?
Thanks in advance.
2009 Aug 18
0
[LLVMdev] ARMSchedule.td MipsSchedule.td etc.
Actually after some digging I managed to answer these questions for myself. I am guessing that this information is used by the Schedule* classes in CodeGen.
--- On Mon, 8/17/09, Carter Cheng <carter_cheng at yahoo.com> wrote:
> From: Carter Cheng <carter_cheng at yahoo.com>
> Subject: [LLVMdev] ARMSchedule.td MipsSchedule.td etc.
> To: llvmdev at cs.uiuc.edu
> Date: