similar to: [LLVMdev] Several basic questions about Builder

On Sun, Jun 28, 2009 at 1:05 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > 1) Using the Builder interface how does one create the equivalent of stack frames and access variables in the current stack frame or perhaps in the static enclosing scope (assuming functions can be nested)? To create stack variables, you can use the alloca instruction; see

I am curious- what is the current status of the MIPS support in LLVM? I have a mipsel device and was wondering if I could compile code for it with clang. Would I have to implement a backend setup myself? Is there also an option to compile w/ clang on an x86 for Mipsel? Thanks in advance.

This is probably another very basic question- but is there a simple method for cross compiling LLVM for another platform? Thanks in advance.

On Mon, Jul 20, 2009 at 4:15 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > This is probably another very basic question- but is there a simple method for cross compiling LLVM for another platform? If you already have a cross-compiling environment set up, it shouldn't be too hard; for LLVM and llvm-gcc, you should be able to pass in --host=mytarget to configure, and if

On Mon, Jul 27, 2009 at 8:56 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > Is there also an option to compile w/ clang on an x86 for Mipsel? A normal build of clang includes limited cross-compile support by passing in the "-ccc-host-triple" option, although it's still a bit of a work-in-progress. Nobody has added support for any Mips targets, but it's really

Hi, I was looking over the experimental MIPS backend and noticed that it has a delay slot pass which just inserts nops into the delay slots. I assume it should be possible to do a bit better than this. Is there an existing pass which "fills" delay slots or would I have to write one if I wanted slightly more optimal code? (anyone have any references?) Thanks in advance.

Hi All, ORC's new concurrent compilation model generates some interesting lifetime and thread safety questions around LLVMContext: We need multiple LLVMContexts (one per module in the simplest case, but at least one per thread), and the lifetime of each context depends on the execution path of the JIT'd code. We would like to deallocate contexts once all modules associated with them have

2012/2/3 Patrik Hägglund <patrik.h.hagglund at ericsson.com>: > Hi, > > I've tracked the first problem (mentioned in my previous email, quoted > below) down further, ending up in the handling of alloca in > LoopRotation.cpp (from trunk): > >      // If the instruction's operands are invariant and it doesn't read > or write >      // memory, then it is

I just looked over your diff and it would seem to me that additional changes would be needed to be done to some of the LLVM-IR -> DAG stuff to make things fully functional (this could be a bit of supposition on my part since I do not fully understand all of the code). --- On Sun, 8/2/09, Andrew Lenharth <andrewl at lenharth.org> wrote: > From: Andrew Lenharth <andrewl at

Thanks both. I looked over the getelementptr and bitcast documentation but I am still a bit confused by one point. lets say i have something like this. union { long Int; double float; long* IntRef; } Since pointer sizes are platform dependent if I am trying to use the union in question with an extern C function is it possible to make write the single definition in a platform independent way?

On Sun, Aug 2, 2009 at 2:06 PM, Carter Cheng<carter_cheng at yahoo.com> wrote: > I was looking over the experimental MIPS backend and noticed that it has a delay slot pass which just inserts nops into the delay slots. I assume it should be possible to do a bit better than this. Is there an existing pass which "fills" delay slots or would I have to write one if I wanted slightly

I apologize if this has been asked before but which classes utilize the information in these files? I am asking since I am trying to extend the MIPS backend to 64bit among other things. Thanks in advance, Carter.

I have a basic question concerning how LLVM assigns labels to the LHS of an SSA assignment. My impression from the interface is you can pick a string which becomes the label for the result. However if you multiple labels which share the same name in a function a number gets added to the end of the label (is this correct?). In cases where you need to know what these resulting labels are is it

On 14 Jan 2013, at 15:48, Reid Kleckner <rnk at google.com> wrote: > > Or maybe would it be possible to have a custom allocator for memory space for the native code that we could provide? With this last option we would be responsible for the clean up ourselves and just provide memory space to LLVM where it can store the results. > > Yes, you should be able to inherit from

Yes. But it is not really being used by most (any?) targets because post-RA scheduling is disabled by default. Also, the existing model is very limited in what types of micro-architectures can be described. I've been extending it to enable scheduling of multi-issue targets, targets with overlapping FU usage, and targets that use and define registers in multiple pipeline stages. See

On Sun, Aug 2, 2009 at 6:09 PM, Carter Cheng<carter_cheng at yahoo.com> wrote: > I just looked over your diff and it would seem to me that additional changes would be needed to be done to some of the LLVM-IR -> DAG stuff to make things fully functional (this could be a bit of supposition on my part since I do not fully understand all of the code). Code generation actually was

Hi all, I am trying to compile a high-level imperative OOP-like language to the LLVM IR. Do we have any "generic" way of translating a non-SSA form to the LLVM IR's SSA? There are lots of LLVM front-ends now. Do they do such translation individually? or there is some common non-SSA IR that we can translate to, and can be converted to the LLVM IR automatically? I did not find such

Hi, I have two problems regarding the llvm.stackrestore intrinsic. I'm running on 3.0, but a quick test on trunk also showed the same behavior. First problem: --------------- I have code like: tmp1 = call llvm.stacksave() tmp2 = alloca [do some stuff with tmp2] call llvm.stackrestore(tmp1) [some other stuff] tmp3 = call llvm.stacksave() tmp4 = alloca [do some stuff

Actually after some digging I managed to answer these questions for myself. I am guessing that this information is used by the Schedule* classes in CodeGen. --- On Mon, 8/17/09, Carter Cheng <carter_cheng at yahoo.com> wrote: > From: Carter Cheng <carter_cheng at yahoo.com> > Subject: [LLVMdev] ARMSchedule.td MipsSchedule.td etc. > To: llvmdev at cs.uiuc.edu > Date:

On Tue, Jun 30, 2009 at 12:16 AM, Carter Cheng<carter_cheng at yahoo.com> wrote: > Since pointer sizes are platform dependent if I am trying to use the union in question with an extern C function is it possible to make write the single definition in a platform independent way? Not really; there's some discussion of that in the thread starting at