similar to: [LLVMdev] Floating point comparison doubt

Displaying 20 results from an estimated 1000 matches similar to: "[LLVMdev] Floating point comparison doubt"

2012 Dec 13
0
[LLVMdev] RTLIB::UO_F32
what C code would produce the following when soft float is enabled? (RTLIB::UO_F32, "__unordsf2"); (RTLIB::UO_F64, "__unorddf2"); (RTLIB::O_F32, "__unordsf2"); (RTLIB::O_F64, "__unorddf2"); tia. reed
2009 Jul 03
2
[LLVMdev] Doubt in PHI node elimination
Hi, In PHI node elimination pass to insert the copy in the predecessor block, there is a check if terminator is not an invoke instruction then place the copy there only. However for invoke terminator instruction a safe position is located for copy insertion. My doubt is why is this safe location search done only for invoke instruction and not for other terminators such as branch.
2009 Jul 03
0
[LLVMdev] Doubt in PHI node elimination
Sachin.Punyani at microchip.com wrote: > > Hi, > > > > In PHI node elimination pass to insert the copy in the predecessor > block, there is a check if terminator is not an invoke instruction > then place the copy there only. However for invoke terminator > instruction a safe position is located for copy insertion. > > > > My doubt is why is this safe
2009 Jul 07
1
[LLVMdev] Doubt in PHI node elimination
On Jul 3, 2009, at 4:01 AM, Sanjiv Gupta wrote: > Sachin.Punyani at microchip.com wrote: >> >> Hi, >> >> >> >> In PHI node elimination pass to insert the copy in the predecessor >> block, there is a check if terminator is not an invoke instruction >> then place the copy there only. However for invoke terminator >> instruction a safe
2009 Dec 11
0
[LLVMdev] Doubt related to scheduling with shift operation
Hi, > My target is an 8-bit target. Therefore while performing a shift (right > or left) on long (32 bits) it is legalized in 4 smaller units. After > performing the shift, this value should be stored at the same location. > So order of the stores does matter. But all 4 stores are parallel in the > code and do not have any control flow dependency between them. Therefore >
2009 Dec 10
2
[LLVMdev] Doubt related to scheduling with shift operation
Hi, For the case, please see the ".ll" file attached. Here I am doing a right shift on 32 bits by constant amount (specifically by 8). My target is an 8-bit target. Therefore while performing a shift (right or left) on long (32 bits) it is legalized in 4 smaller units. After performing the shift, this value should be stored at the same location. So order of the stores does
2008 Dec 18
2
[LLVMdev] Doubts about lowering of UMUL_LOHI
Hi, When expanding multiply operation in LegalizeTypes LLVM generates some nodes such as UMUL_LOHI (please refer file LegalizeIntegerTypes.cpp - function - ExpandIntegerResult). However while lowering this operation in LegalizeDAG (please refer file LegalizeDAG.cpp - function - LegalizeOp) the comment says "These nodes will only be produced by target-specific lowering.....".
2009 Dec 15
2
[LLVMdev] Crash in PBQP register allocator
Hi Lang, Thanks for your inputs on the problem. I was just curious to know if you got any opportunity to work on the solution for this. Regards Sachin > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Sachin.Punyani at microchip.com > Sent: Tuesday, November 17, 2009 12:00 PM > Subject: Re: [LLVMdev] Crash
2009 Jan 28
2
[LLVMdev] AsmPrinter question
Hi, Probably I did not mention my question correctly. I need to emit declarations of the libcalls (that are made in the current module) at the beginning of the assembly file. The class "Module" does not maintain any list of the libcalls made during the program. Although, it maintains lists of all the global variables and functions in the current module. Traversing each
2012 Dec 14
0
[LLVMdev] RTLIB::UO_F32
Hi Reed, Sorry about the off-list reply. I need to reset my list preferences. If I build: cmp.c: int cmp_single(float a) { return (a != a) ? 1 : 0; } int cmp_double(double a) { return (a != a) ? 1 : 0; } with clang -target mips-unknown -S cmp.c I get calls to __unordsf2 and __unorddf2. Pete
2010 Jan 26
3
[LLVMdev] Crash in PBQP register allocator
Hi Sachin, llvm-dev, I've just committed a new PBQP solver which, among other things, should take care of this bug. Please let me know how it works out for you. Cheers, Lang. On Tue, Dec 15, 2009 at 5:54 PM, Lang Hames <lhames at gmail.com> wrote: > Hi Sachin, > > Yes. Bernhard Scholz and I have just discussed a fix for this. I hope to > commit it in the next few days. I
2008 Dec 18
0
[LLVMdev] Doubts about lowering of UMUL_LOHI
On Wed, Dec 17, 2008 at 11:49 PM, <Sachin.Punyani at microchip.com> wrote: > 2) Why is custom legalization of this node not allowed? No target has needed it so far. Why do you need it? > 3) My target does not have any instruction directly matching to this > operation. How should this node be legalized? If your target doesn't have this operation, you should mark
2009 Dec 15
0
[LLVMdev] Crash in PBQP register allocator
Hi Sachin, Yes. Bernhard Scholz and I have just discussed a fix for this. I hope to commit it in the next few days. I will let you know as soon as it goes in to the mainline. Regards, Lang. On Tue, Dec 15, 2009 at 5:34 PM, <Sachin.Punyani at microchip.com> wrote: > Hi Lang, > > Thanks for your inputs on the problem. I was just curious to know if you > got any opportunity to
2009 Nov 15
2
[LLVMdev] Crash in PBQP register allocator
Hi Sachin, Confirmed: This is being caused by a subtle issue in the heuristic PBQP solver. Specifically: R1/R2 reductions as currently implemented can, on rare occasions, lead to the heuristic solver failing to find a finite cost solution, even though one exists. The infinite cost solution will always be in violation of some rule of register allocation (failing to handle an interference, or
2008 Sep 19
3
[LLVMdev] Illegal pointer type
> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Bill Wendling > Sent: Friday, September 19, 2008 4:38 AM > > On Thu, Sep 18, 2008 at 7:12 AM, <Sachin.Punyani at microchip.com> wrote: > > What changes would be required in LLVM to support illegal pointer type? > > > Hi Sachin, >
2009 Jan 29
0
[LLVMdev] AsmPrinter question
Hi Sachin, The declaration of functions called via the "call" instruction is a GlobalValue in your Module. You can go through all of the GlobalValues, look for those that are Function declarations (use the "Function::isDeclaration()" method), and then placing them in the appropriate place in your assembly file. Would that work? -bw On Jan 28, 2009, at 12:23 AM,
2009 Nov 17
0
[LLVMdev] Crash in PBQP register allocator
Thanks Lang! I think we can use linear scan as work around for short term. Thanks for your help. Regards Sachin > -----Original Message----- > From: Lang Hames [mailto:lhames at gmail.com] > Sent: Sunday, November 15, 2009 10:08 AM > To: Sachin Punyani - I00202 > Cc: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Crash in PBQP register allocator > > Hi Sachin, >
2009 Jan 30
1
[LLVMdev] AsmPrinter question
> Hi Sachin, > > The declaration of functions called via the "call" instruction is a > GlobalValue in your Module. You can go through all of the > GlobalValues, look for those that are Function declarations (use the > "Function::isDeclaration()" method), and then placing them in the > appropriate place in your assembly file. > > Would that work? Hi
2008 Aug 19
2
[LLVMdev] Type Legalizer - Load handling problem
On Mon, 2008-08-18 at 08:50 -0700, Eli Friedman wrote: > On Mon, Aug 18, 2008 at 6:31 AM, <Sachin.Punyani at microchip.com> wrote: > > assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && > > "Invalid operand expansion"); > > > > LOAD node has two values but the assertion checks N->getNumValues() == 1 >
2008 Sep 19
0
[LLVMdev] Illegal pointer type
I am assuming a 16-bit value will be stored in a pair of 8-bit registers? If so, add pseudo register which represent pairs of 8-bit registers. Add them to a pseudo register class. This allows you to mark i16 "legal". The difficult part is then to figure out how to lower these 16-bit operations into 8-bit ones. You probably need to custom lower a bunch of them with target