similar to: [LLVMdev] possible PowerPC (32bits) backend bug

Sebastian Pop wrote: > same mechanism could be useful. It would be nice to be able to write this: > > def insn : Inst<(outs i32:$dst), (ins i32:$src1, i32:$src2), > "some assembler", > [(set $dst, (Op $src1, $src2))]>; >From the PPC changes, I see that this is already possible under a slightly different form: def FSUBS :

Hi, I have a small network with several Windows XP clients and an Ubuntu server (7.10) running Samba (3.0.26) as a Domain Controller but can't get the clients to login to the domain. Here's my smb.conf: [global] name resolve order = wins lmhosts host bcast idmap gid = 10000-20000 passwd chat = *Enter\snew\sUNIX\spassword:* %n\n *Retype\snew\sUNIX\spassword:* %n\n

Example: target triple = "powerpc64le-unknown-linux-gnu" define void @TestFoo() { entry_bb: br label %loop_bb loop_bb: %tmp = load float, float* undef %tmp1 = fmul float %tmp, 0x401F25E360000000 %tmp2 = fadd float %tmp1, 0x3FC1A7B960000000 %tmp3 = select i1 undef, float 0x401F25E360000000, float %tmp2 store float %tmp3, float* undef br label %loop_bb } The code above is

Hola, Estoy intentando realizar un ajuste a un modelo setar con R y me surgen problemas a la hora de representar el modelo setar sin la constante. El código es el siguiente: # Estimacion TAR(2;2,2) con delta 1: mod.setar <- setar(x, m = 2, mL = 2, mH = 2, thDelay = 1) mod.setar summary(mod.setar) mod.setarc<-setar(x, m=2, mL=2, mH=2, thDelay=1, include=c("none")) ##eliminamos

On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote: > On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: > > > > On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > > > > > Here's my "thought experiment" (from PR11589): I have a bunch of > > > load-fadd-store chains to schedule. A store takes two cycles to > > > clear > >

On Dec 20, 2011, at 10:29 AM, Hal Finkel wrote: > On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote: >> On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: >>> >>> On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: >>> >>>> Here's my "thought experiment" (from PR11589): I have a bunch of >>>> load-fadd-store chains to

On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote: > > On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote: > > > Here's my "thought experiment" (from PR11589): I have a bunch of > > load-fadd-store chains to schedule. A store takes two cycles to > > clear > > its last pipeline stage. The fadd takes longer to compute its result > > (say 5

Am 18.11.2014 um 05:03 schrieb Ilia Mirkin: > For values above integer accuracy in floats, val - floor(val) might > actually produce a value greater than 1. For such large floats, it's > reasonable to be imprecise, but it's unreasonable for FRC to return a > value that is not between 0 and 1. > > Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> > --- >

Am 18.11.2014 um 15:05 schrieb Ilia Mirkin: > On Tue, Nov 18, 2014 at 8:54 AM, Roland Scheidegger <sroland at vmware.com> wrote: >> Am 18.11.2014 um 05:03 schrieb Ilia Mirkin: >>> For values above integer accuracy in floats, val - floor(val) might >>> actually produce a value greater than 1. For such large floats, it's >>> reasonable to be imprecise,

For values above integer accuracy in floats, val - floor(val) might actually produce a value greater than 1. For such large floats, it's reasonable to be imprecise, but it's unreasonable for FRC to return a value that is not between 0 and 1. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 3 ++- 1 file changed, 2

On 18/11/14 14:34, Roland Scheidegger wrote: > Am 18.11.2014 um 15:05 schrieb Ilia Mirkin: >> On Tue, Nov 18, 2014 at 8:54 AM, Roland Scheidegger <sroland at vmware.com> wrote: >>> Am 18.11.2014 um 05:03 schrieb Ilia Mirkin: >>>> For values above integer accuracy in floats, val - floor(val) might >>>> actually produce a value greater than 1. For such

On Tue, Nov 18, 2014 at 8:54 AM, Roland Scheidegger <sroland at vmware.com> wrote: > Am 18.11.2014 um 05:03 schrieb Ilia Mirkin: >> For values above integer accuracy in floats, val - floor(val) might >> actually produce a value greater than 1. For such large floats, it's >> reasonable to be imprecise, but it's unreasonable for FRC to return a >> value that

Hi, I have a task to complete and I'm getting stuck. I can't find anything comparable in the documentation. The shortest explanation I can give is as follows: I need to use double-precision floating point values for floating-point multiplies. I'll not go into why: That would take the discussion away from the essential problem. E.g. Replace: fmuls %f20,%f21,%f8 with the

Quitar la constante del modelo, no parece una buena estrategia para estos datos. En cualquier caso, si quieres visualizar las predicciones del modelo setarc con las de los demás modelos, prueba sustituir la linea plot(x.test, ylim = range(x)) por plot(x.test, ylim = range( union( x , frc.test[["setarc"]] ))) Un saludo. Olivier -- ____________________________________ Olivier G.

I haven't been able to find any help on this and am really struggling. I've been using RODBC 1.1-3 and R(D)COM v1.35 for a little over a year successfully with my Access Database, and now im switching to Oracle 9i. I use R 2.0.1 on a Windows XP platform, 1GB ram, 2GHz Intel Processor) When I connect through the Rgui R console, the connection is successful (but through VB the attempt

F.Y.I >>> "Tian, Kevin" <kevin.tian@intel.com> 08.11.27. 11:50 >>>Sorry for a typo. I did mean domU instead of dom0. :-) The point here is that time_resume will sync to new system time and wall clock at restore, and thus pv guest should be able to continue... Xen system time is not wallclock time which just counts up from power up. As Keir points out, only its

Hi, I find PV domin hung, When we take those steps 1, save PV domain 2, change system time of PV domain back 3, restore a PV domain or 1, migrate a PV domain from Machine A to Machine B 2, the system time of Machine B is slower than Machine A. the problem is wc_sec will be change when system-time chanaged in dom0 or restore in a

Hi All, Recently I was doing some AArch64 work and noticed some cases where fmuls were not getting fused with fadds. Is there any particular reason that the AArch64 machine combiner doesn't do this like it does for add/mul? I am happy to work up a patch for this, but I wanted to make sure that there wasn't a good reason for it not already being there. FWIW, I see where GCC is doing

Hi, I'm probably being fairly stupid. But I did the following, starting with the following two files: # tcprobe -i vts_01.m2v [tcprobe] MPEG elementary stream (ES) [tcprobe] summary for vts_01.m2v, (*) = not default, 0 = not detected import frame size: -g 720x576 [720x576] aspect ratio: 16:9 (*) frame rate: -f 25.000 [25.000] frc=3 # tcprobe -i vts_01.m2a

Dear all: To write a compiler for Microsoft Direct3D shaders from our hardware, I have a program which translates the Direct3D shader assembly to LLVM assembly. I added several intrinsics for this purpose. It's a vector ISA and has some special instructions like: * rcp (reciprocal) * frc (the fractional portion of each input component) * dp4 (dot product) * exp (exponential) * max, min These