similar to: [LLVMdev] assertion in LeakDetector

On Wed, Jun 3, 2009 at 5:10 PM, Manjunath Kudlur <keveman at gmail.com> wrote: > I am seeing the following assertion in leak detector. > > /llvm/lib/VMCore/LeakDetector.cpp:43: > void<unnamed>::LeakDetectorImpl<T>::addGarbage(const T*) [with T = > void]: Assertion `Ts.count(Cache) == 0 && "Object already in set!"' > failed. > > I am

Hi Bill, I am using the following version of BuildMI : MachineInstrBuilder BuildMI(MachineFunction &MF, const TargetInstrDesc &TID, unsigned DestReg) I do the following : void createInstrs(std::vector<MachineInstr *>& ilist) { Machine Instr *mi; mi = BuildMI(MF, someTID, somereg);

Hello, I am writing a MachineFunction pass that converts vector instructions to a sequence of scalar instructions. First, I go through the function and look for vector registers. For each vector register, I create a set of corresponding scalar registers using createVirtualRegister() function and put it in a map. Then I go through the function and replace vector instructions.The basic structure of

On Wed, Jun 3, 2009 at 12:46 PM, Manjunath Kudlur<keveman at gmail.com> wrote: > Hello, > > I am writing a MachineFunction pass that converts vector instructions > to a sequence of scalar instructions. Why? That really isn't the level you want to be doing that sort of thing normally. Usually, legalization turns illegal vector operations into legal scalar operations. -Eli

I am trying to JIT some code containing an indirect branch (and the corresponding store i8* blockaddress(@label)). I am using LLVM 2.7 code base. I build the ExecutionEngine using EngineBuilder, and call engine->getPointerToFunction(func). When I use setOptLevel(llvm::CodeGenOpt::None), the JITing fails with the following message : JIT.h:131: virtual void*

> On 2014 Dec 10, at 14:08, Tom Stellard <tom at stellard.net> wrote: > > On Wed, Dec 10, 2014 at 11:21:08AM -0800, Duncan P. N. Exon Smith wrote: >> >>> On 2014 Dec 10, at 08:40, Tom Stellard <tom at stellard.net> wrote: >>> >>> On Tue, Dec 09, 2014 at 09:22:16PM -0800, Duncan P. N. Exon Smith wrote: >>>> The `Metadata`/`Value`

> On 2014 Dec 10, at 08:40, Tom Stellard <tom at stellard.net> wrote: > > On Tue, Dec 09, 2014 at 09:22:16PM -0800, Duncan P. N. Exon Smith wrote: >> The `Metadata`/`Value` split (PR21532) landed in r223802 -- at least, the >> C++ side of it. This was a rocky day, but I suppose that's what I get >> for failing to stage the change in smaller pieces. >>

On Wed, Dec 10, 2014 at 05:27:45PM -0800, Duncan P. N. Exon Smith wrote: > +zalman at google.com > Hi Duncan, This patch plus another small change fixes the assertion failure for me. With the patch alone, the void* overload of addGarbageObject() was being used by MDNode::getTemporary(), so I had to cast the object as an MDNode*: diff --git a/lib/IR/Metadata.cpp b/lib/IR/Metadata.cpp

Dan, Thanks a lot. Using a modifier in the assembly string works for this case. I am trying to solve a related problem. I am trying to print out a set of "mov" ops for the vector_shuffle node. Since the source of the "mov" is from one of the sources to vector_shuffle, depending on the mask, I am not sure what assembly string to emit. For example, if I have d <-

I committed: r224058 = 966942da9e68b59c31ce770e7f94c55a63482c6b r224060 = da75f7277e3a129aed8ef8aa4e0d84de40b76fd4 r224061 = f88e4c8e9171045454b2c8e05054c2af8da3fe4f Let me know if somehow you're still hitting the problem. r224061 removes leak detection entirely from `MachineInstr`. There aren't any leaks to be had there, since they're allocated in a custom allocator. They're

Hello, I am trying to create a machine instruction for "extractelement". I want to translate r <- extractelement v, 0 to mov r, v.x I was looking at the dag I can use and I found vector_extract. The inputs for this SDnode are a register and a iPtr constant. With that, I need to create 4 separate def's to extract element 0, 1, 2, and 3 and translate to v.x, v.y, v.z, and v.w. I

Manjunath, I had a very similar problem and I solved it using a custom vector shuffle and addition instead of mov. For example, Vector_shuffle s1, s2, <0,3> is mapped to a custom instruction where I transform the swizzle to a 32bit integer mask and an inverted mask. So I have dst, src0, src1, imm1, imm2 And I have my asm look similar to: Add dst, src0.imm1, src1.imm2 and then in the asm

Hi, Has anyone had any success with running different PassManagers on llvm::Modules they've already JITed and are executing? In detail: 1) getting the IR, in form of an llvm::Module 2) calling PassManager->run() on the module 3) calling getFunction() and getPointerToFunction() to JIT the module 4) executing the JITed code using the function pointer received in step 3 and then what I

I want to add a set of "properties" to each instruction in my instruction set, and want to be able to query that in my machine-specific optimizations. My Insts.td file looks as follows : class InstProperty; def propX : InstProperty; def propY : InstProperty; def propZ : InstProperty; class myInst<..., list<InstProperty> props> : Instruction { ... ...

The `Metadata`/`Value` split (PR21532) landed in r223802 -- at least, the C++ side of it. This was a rocky day, but I suppose that's what I get for failing to stage the change in smaller pieces. As of r223916 (lldb), I'm not aware of any remaining (in-tree) breakage, so if I've missed some problem in the sea of buildbot errors, please flag me down. I'll follow up soon with

One way to do this is to handle this in the AsmPrinter, with operand modifiers. For example, on x86 there are instructions with ${dst:call} in their asm string. The "call" part is interpreted as an operand modifier. The assembly printer looks for the "call" modifier on MachineOperand::MO_Immediate operands (in X86ATTAsmPrinter::printOperand), which lets it perform custom

Hi, I found the following wiki page in the Unladen Swallow project: http://code.google.com/p/unladen-swallow/wiki/CodeLifecycle This would appear to answer my question. Could someone confirm for me if it's definitely unsafe to attempt to optimise/JIT any Modules while a different thread is currently executing a JITed function which has been generated from them? Or am I just missing

Manjunath, I asked this question recently, but instead of telling you to search the archive I'm going to take it as a chance to recall how to do it (because I'll do so anyway and even telling tablegen to use an enum for instructions is not as trivial to do as you might think : ) I wrote it up in the wiki at http://wiki.llvm.org/HowTo:_Add_arbitrary_properties_to_instructions Regards,

Christian, Thanks for your reply and the wiki entry. I did search the archives, but evidently I didn't search for the right thing. My bad. Anyways, I am still wondering about the other part of my question. Why aren't there Tablegen backends specific to some architecture backends? Let me describe a different scenario. Suppose my architecture has vector and scalar units, and suppose I want

Hello, I am trying to convert the subtree (vector_shuffle v2f32, v2f32 (build_vector imm1, imm2)) to a machine instruction that takes 2 v2f32's and 2 immediates. I tried the following table gen pattern : (set v2f32Reg:$dst, (vector_shuffle v2f32Reg:$src1, v2f32Reg:$src2, (build_vector imm:$c1, imm:$c2))) Table gen barfs about type