similar to: [LLVMdev] RFC: AVX Feature Specification

On Apr 30, 2009, at 3:02 PM, David Greene wrote: > I've been working on adding AVX to LLVM and have run across a number > of > questions. Here's the first one. > > In some ways AVX is "just another" SSE level. Having AVX implies > you have > SSE1-SSE4.2. However AVX is very different from SSE and there are a > number > of sub-features which

On 30-Apr-09, at 6:38 PM, Dan Gohman wrote: > On Apr 30, 2009, at 3:02 PM, David Greene wrote: >> As I've been going along I've added feature flags for SSE4a and >> SSE5. These >> really do need to be separate feature flags because having SSE4a and/ >> or SSE5 >> does not imply that you have SSE4.2 or SSE4.1. So they can't be >> part of the

These patches fix a few compiler warnings. Tested on top of commit aee0dc5565711ef5be7c30fb5fc1c5f3f98db09f Jonathan Boeing (6): Use z width specifier when printing size_t variable pxe: fix truncation warning gpllib: fix sizeof(char *) misuse hdt: fix sizeof(char *) misuse hdt: fix sizeof(char *) misuse hdt: fix sizeof(char *) misuse com32/gpllib/dmi/dmi.c | 24 +++---

The code was passing sizeof(char *) - not the length of the buffer - to memset. Change the function to take the length of the buffer as a parameter. Fixes the warning: argument to 'sizeof' in 'memset' call is the same expression as the destination; did you mean to provide an explicit length? Signed-off-by: Jonathan Boeing <jonathan.n.boeing at gmail.com> ---

----- Original Message ----- From: "Jon Harrop" <jon at ffconsultancy.com> To: <llvmdev at cs.uiuc.edu> Sent: Sunday, June 21, 2009 2:51 PM Subject: [LLVMdev] SSE examples > > Does anyone have any LLVM IR examples implementing things using the > instructions for SSE, like complex arithmetic or 3D vector-matrix stuff? > I don't have any examples... >

Does anyone have any LLVM IR examples implementing things using the instructions for SSE, like complex arithmetic or 3D vector-matrix stuff? I'd like to have HLVM use them "under the hood" for some things but I cannot see all of the operations that I was expecting (e.g. dot product) and am not sure what works when (e.g. "Not all targets support all types however."). --

Package: xen-utils-4.0 Version: 4.0.1-1 Severity: wishlist [resending from another address since my ISP seems to be queueing emails for up to 25 hours and counting...] I did some experiments with the xen remus HA system. With overlord3:~$ debdiff xen_4.0.1-1.dsc xen_4.0.1-1lindi1.dsc diff -Nru xen-4.0.1/debian/rules.real xen-4.0.1/debian/rules.real --- xen-4.0.1/debian/rules.real 2010-08-02

Package: xen-utils-4.0 Version: 4.0.1-1 Severity: wishlist I did some experiments with the xen remus HA system. With overlord3:~$ debdiff xen_4.0.1-1.dsc xen_4.0.1-1lindi1.dsc diff -Nru xen-4.0.1/debian/rules.real xen-4.0.1/debian/rules.real --- xen-4.0.1/debian/rules.real 2010-08-02 16:10:13.000000000 +0300 +++ xen-4.0.1/debian/rules.real 2011-01-05 00:32:41.000000000 +0200 @@ -159,6 +159,7 @@

Hi all, I have a sample test case : $ cat 1.c int foo(int x, int y){ int z = x + y; return z/2; } I tried to get its IR form with clang providing subtarget feature as mmx for target x86_64 $ clang -O3 -mmmx 1.c -S -emit-llvm in the IR generated i can see the subtarget-features as function attribute : "target-features"="+mmx" In the SelectionDAG phase in file

Thanks Kevin for the reply. I got the point now :) On 10 Apr 2015 00:18, "Smith, Kevin B" <kevin.b.smith at intel.com> wrote: > For x86_64 ABI, a minimum feature set of SSE2 is required. > > > > Kevin > > > > *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On > Behalf Of *suyog sarda > *Sent:* Thursday, April 09,

On Thu, 24 May 2012, Hal Finkel wrote: > Henning, > > I believe the code that is supposed to do this is in: > lib/Target/X86/X86Subtarget.cpp in > X86Subtarget::AutoDetectSubtargetFeatures() > Is there a bug in that function? I read there: // FIXME: AVX codegen support is not ready. //if ((ECX >> 28) & 1) { X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); }

Henning, I believe the code that is supposed to do this is in: lib/Target/X86/X86Subtarget.cpp in X86Subtarget::AutoDetectSubtargetFeatures() Is there a bug in that function? -Hal On Thu, 24 May 2012 23:56:48 +0200 (CEST) Henning Thielemann <llvm at henning-thielemann.de> wrote: > > On Thu, 24 May 2012, Pan, Wei wrote: > > > Very likely AVX is not enabled in your llc.

Hey Evan, At the point of the instructions you suggested I step through, X86ISelLowering has this state: - this 0x00000000005fe728 {VarArgsFrameIndex=-842150451 RegSaveFrameIndex=-842150451 VarArgsGPOffset=3452816845 ...} llvm::X86TargetLowering * const + llvm::TargetLowering {TM={...} TD=0x00000000008edac0

Hi Jakob, I have been trying to learn how the CodeGen passes work and I am playing around with the -debug-pass option. I tried implementing a bare CallGraphSCCPass based Pass in the CodeGen which basically does nothing for now. I mostly tried to replicate what RegAlloc passes do. I did this instead of modifying the existing RegAlloc passes to use CallGraphSCCPass because that was becoming way too

On Oct 31, 2012, at 1:41 PM, Madhusudan C.S <madhusudancs at gmail.com> wrote: > I have spent last 4 weeks trying to figure out how to implement > Interprocedural Register Allocation. I must admit that I was really > overwhelmed with LLVM's codebase while trying to figure this out :) > There is so much to know! I think I have reached a point where I > have some sort of

Henning, Are you looking at trunk? I believe that in trunk this has been uncommented. -Hal On Fri, 25 May 2012 00:47:42 +0200 (CEST) Henning Thielemann <llvm at henning-thielemann.de> wrote: > > On Thu, 24 May 2012, Hal Finkel wrote: > > > Henning, > > > > I believe the code that is supposed to do this is in: > > lib/Target/X86/X86Subtarget.cpp in >

On Feb 12, 2008, at 5:26 PM, Chuck Rose III wrote: > Hola LLVMers, > > I’m debugging through some strangeness that I’m seeing on X64 on > windows with LLVM2.2. I had to change the code so that it would > engage the x64 target machine on windows builds, but I’ve otherwise > left LLVM 2.2 alone. The basic idea is that I’ve got a function bar > which is compiled by

Hey all, I am trying to implement a new subtarget for the X86 target that has only 64 bit registers and instructions and a very minimal ISA excluding any FPU instructions etc. I have made the required changes to the instructions such that all the instructions that I don't wish to use have a required<> clause that precludes them from being utilised when compiling for this subtarget.

Hola LLVMers, I'm debugging through some strangeness that I'm seeing on X64 on windows with LLVM2.2. I had to change the code so that it would engage the x64 target machine on windows builds, but I've otherwise left LLVM 2.2 alone. The basic idea is that I've got a function bar which is compiled by VStudio and I'm creating another function foo via LLVM JIT which is going

Hi Nadav, Thanks for the quick reply !! Ok, so as of now we are lacking capability to handle flat large reductions. I did go through function vectorizeChainsInBlock() (line number 2862). In this function, we try to vectorize if we have phi nodes in the IR (several if's check for phi nodes) i.e we try to construct tree that starts at chains. Any pointers on how to join multiple trees? I